Kawasaki KS152JB, 80C152, 80C51 Interrupts, Timer/Counter 0 in Mode, IE Interrupt Enable Register

Page 15

KS152JB Universal Communications Controller Technical Specifications

Mode 3 is used in cases where an extra 8 bit timer is needed. With Timer 0 in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3. It can also be used as a baud rate generator for the serial port.

OSC

 

S3P1

C/T

T0 pin

TR0

GATE

INT0 pin

I0

I1

S3P1

TR1

Q

TL0

5 bits

TH0

8 bits

TF0

TF1

INTERRUPT

INTERRUPT

Timer/Counter 0 in Mode 3

2.8 Interrupts

The cpu has a provision for 11 different interrupt sources. These are the two external interrupts, the three timer interrupts, the local serial port interrupt, dma interrupt and global serial port inter- rupts.

 

7

6

5

 

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EA

--

--

 

ES

ET1

EX1

ET0

EX0

 

 

 

 

 

 

 

 

 

 

 

 

EA

Global Disable bit. If this bit is cleared it disables all the interrupts at once.

 

If EA is 1 then interrupts can be individually enabled/disabled by setting or

 

clearing its own enable bit.

 

 

 

 

 

 

--

reserved.

 

 

 

 

 

 

 

 

 

ES

Local Serial port interrupt enable.

 

 

 

 

 

ET1

Timer 1 interrupt enable.

 

 

 

 

 

 

EX1

External interrupt 1 enable.

 

 

 

 

 

 

ET0

Timer 0 interrupt enable.

 

 

 

 

 

 

EX0

External interrupt 0 enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IE: Interrupt Enable Register.

The External Interrupts INT0 and INT1 can be either edge triggered or level triggered, depending on bits IT0 and IT1. The bits IE0 and IE1 in the TCON register are the flags which are checked to generate the interrupt. When an interrupt is generated by these external interrupt inputs, they will be cleared on entering the Interrupt Service routine, only if the interrupt type is edge triggered. In

Kawasaki LSI USA, Inc.

Page 15 of 120

Ver. 0.9 KS152JB2

Page 14 Page 16
Image 15
Page 14 Page 16
Contents Introduction Technical Specifications Pin Name Alternate Function Pin DescriptionPIN Description Name Description PortXTAL1 XTAL2RST Epsen ALEPsen EbenSFR map for the cpu Special function RegistersReset Timing Reset Values of the SFRs Pcon ConfigurationsScon Sbuf Indeterminate TmodPort bit I/O Pads Port 0 I/O Pad Port 2 I/O PadPorts 4,5 Fetch via ProgramPsen Epsen CommentsTmod Timer/Counter Mode Control Register TIMER/COUNTERSMode Tcon Timer/Counter Control RegisterTimer/Counter in Mode Timer/Counter 0 in Mode IE Interrupt Enable RegisterInterrupts Priority Level Structure Pgste PDMA1 Pgstv PDMA0 Pgsre Pgsrv Egste EDMA1 Egstv EDMA0 Egsre EgsrvEgsrv 2BH PX0EX0 PgsrvET1 1BH PDMA1EDMA1 PT1Kawasaki LSI USA, Inc Ver .9 KS152JB2 Power Down and Idle Status of the External Pins during Idle and Power DownALE Psen Smod IDL Pcon Power Control RegisterLocal Serial Channel Controller Local Serial Port ModeSerial Port Mode Mode Load Sbuf Baud Rates Timer 1 generated commonly used Baud rates SmodMHZ SINGLE-STEP Operation JNBReti Kawasaki LSI USA Inc Introduction Global Serial ChannelDC JAM CRC 11/IDLE CRC None11/IDLE Csma SdlcExternal clock Internal clock Control cpu Control dma Raw Receive Raw Transmit CSMA/CD Overview CSMA/CD Frame FormatPreamble BOF Address Info CRC EOF Kawasaki LSI USA, Inc Ver .9 KS152JB2 23 24 Interframe Space Jitter Tolerance CSMA/CD Data EncodingManchester Encoding BIT Time Collision DetectionNarrow Pulses Missing 0-to-1 TransitionUnexpected 1-to-0 Transition Tfifo Resolution of CollisionsGSC Inactive Response to a Detected Collision What the GSC was doingBackoff DCRAlgorithm Random Backoff Prbs Tcdcnt Load Bkoff Slot Clock MyslotBKOFF= Myslot Deterministic Backoff Hardware Based Acknowledge Kawasaki LSI USA, Inc Ver .9 KS152JB2 BOF Address Control Info CRC EOF Sdlc Frame FormatKawasaki LSI USA, Inc Ver .9 KS152JB2 Data Encoding Nrzi BIT TimeBIT STUFFING/STRIPPING Sending Abort Character Line IdleAcknowledgement Ring Network PRIMARY/SECONDARY StationsPoint-to-point Network Multi-Drop NetworkUser Defined Protocols Using a Preamble in SdlcHDLC/SDLC Comparison Sdlc HdlcPlanning for Network Changes and Expansions Line DisciplineDMA Servicing of GSC Channels Kawasaki LSI USA, Inc Ver .9 KS152JB2 Baud Rate Initialization External Driver Interface Test ModesJitter Receive Transmit Waveforms Local Value Manchester Encoding BIT TimeReceive Sampling Rate Received BIT Time ReceivedCSMA/CD Clock Recovery Receiver Clock RecoveryAddressing Determining Receiver ErrorsExternal Clocking Rcbat Crce2 CPU/DMA Control of the GSC Determining Line DisciplineCollisions and Backoff What the GSC was doing Response Successful Ending of Transmissions and Receptions GSC Register DescriptionsPL1 PL0 Length Bits GMOD84H Xtclk PL1 PL0Kawasaki LSI USA, Inc Ver .9 KS152JB2 ARB REQ Garen Xrclk Gfien IDL DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc Ver .9 KS152JB2 LNI Noack Tcdt TDN Tfnf TEN DMA Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA with the 80C152 DMA OperationDMA Registers SAS ISA Alternate Cycle ModeBurst Mode DAS IDAExternal Demand Mode Serial Port Demand ModeDMA Transfer from Internal Memory to Internal Memory Timing Diagrams12 OSC.PERIODS ALE Psen P1 Inst Float PCH P2 SFR DMA Cycle Resume Program Execution12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCH DMA Cycle 12 OSC. Periods Resume Program Execution ALE PsenDMA Cycle Resume Program Execution Request Mode Arbiter ModeHold/Hold Acknowledge ARB REQ Using the HOLD/HLDA AcknowledgeALE ARB If Hlda = ALE AEQ ALE REQ Internal Logic of the ArbiterDmxrq Internal Logic of the Requester DMA Arbitration Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Arbitration with Hold/Hold Ack DAS IDA SAS ISA Done Summary of DMA Control BitsInterrupt Structure IE0 ET1 EX1 ET0 EX0 TI+RIIPN1 PT1 PX1 PT0 PX0Transmit Error Flags Logic for Clearing TEN, Setting TDN GSC Transmitter Error ConditionsGSC Receiver Error Conditions Glossary Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCON0/1 092H,093H Xtclk PL1 PL0 Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2 PT1 PX1 PT0 EX0 Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Smod ARB REQ Garen Xrclk Gfien IDL OVR Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 SM0 SM1 SM2 REN TB8 RB8Gate Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2 DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0 PortStack Pointer Data Pointer LOWDPH Timer ControlData Pointer High DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0Timer 1 LSB Timer Mode ControlGate Timer Timer 0 LSBTimer 1 MSB Timer 0 MSBSBUF.7 Serial Port ControlSM0 Serial Data BufferRS1 RS0 Program Status WordACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 AccumulatorKawasaki LSI USA, Inc 119 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2
Top Page Image Contents