Kawasaki 80C51 GSC Register Descriptions, Successful Ending of Transmissions and Receptions

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KS152JB Universal Communications Controller Technical Specifications

would be one interframe space period after the line is sensed as being idle.

As the number of stations approach 256 the probability of a successful transmission decreases rapidly. If there are more than 256 stations involved in the collision there would be no resolution since at least two of the stations will always have the same backoff interval selected.

All the stations monitor the link as long as that station is active, even if not attempting to transmit. This is to ensure that each station always defers the minimum amount of time before attempting a transmission and so that addresses are recognized. However, the collision detect circuitry operates slightly differently.

In normal back-off mode, a transmitting station always monitors the link while transmitting. If a collision is detected one or more of the transmitting stations apply the jam signal and all transmit- ting stations enter the back-off algorithm. The receiving stations also constantly monitor for a col- lision but do not take part in the resolution phase. This allows a station to try to transmit in the middle of a resolution period. This in turn may or may not cause another collision. If the new sta- tion trying to transmit on the link does so during an unused slot time then there will probably not be a collision. If trying to transmit during a used slot time, then there will probably be a collision. The actions the receiver does take when detecting a collision is to just stop receiving data if data has not been loaded into RFIFO or to stop reception, clear receiver enable (REN) and set the receiver abort flag (RCABT - RSTAT.6).

If deterministic resolution is used, the transmitting stations go through pretty much the same pro- cess as in normal back-off, except that the slots are predetermined. All the receivers go through the back-off algorithm and may only transmit during their assigned slot.

3.6.4 SUCCESSFUL ENDING OF TRANSMISSIONS AND RECEPTIONS

In both CSMA/CD and SDLC modes, the TDN bit is set and TEN cleared at the end of a success- ful transmission. The end of the transmission occurs when the TFIFO is empty and the last byte has been transmitted. In CSMA/CD the user should clear the TCDCNT register after successful transmission.

At the end of a successful reception, the RDN bit is set and GREN is cleared. The end of reception occurs when the EOF flag is detected by the GSC hardware.

3.7 GSC Register Descriptions

ADR0,1,2,3 (95H, 0A5H, 0B5H, 0C5H) - Address Match Registers 0,1,2,3 - Contains the address match values which determines which data will be accepted as valid. In 8 bit addressing mode, a match with any of the four registers will trigger acceptance. In 16 bit addressing mode a match with ADR1:ADR0 or ADR3:ADR2 will be accepted. Addressing mode is determined in GMOD(AL).

AMSK0,1 (0D5H, 0E5H) - Address Mask 0,1 - Identifies which bits in ADR0,1 are “don’t care”

Kawasaki LSI USA, Inc.

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Ver. 0.9 KS152JB2

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Contents Introduction Technical Specifications Pin Description PIN DescriptionName Description Port Pin Name Alternate FunctionRST XTAL1XTAL2 ALE PsenEben EpsenSpecial function Registers SFR map for the cpuReset Timing Reset Values of the SFRs Configurations SconSbuf Indeterminate Tmod PconPort 0 I/O Pad Port 2 I/O Pad Port bit I/O PadsPorts 4,5 Program Psen EpsenComments Fetch viaTIMER/COUNTERS Tmod Timer/Counter Mode Control RegisterTcon Timer/Counter Control Register ModeTimer/Counter in Mode Interrupts Timer/Counter 0 in ModeIE Interrupt Enable Register Priority Level Structure Egste EDMA1 Egstv EDMA0 Egsre Egsrv Pgste PDMA1 Pgstv PDMA0 Pgsre PgsrvPX0 EX0Pgsrv Egsrv 2BHPDMA1 EDMA1PT1 ET1 1BHKawasaki LSI USA, Inc Ver .9 KS152JB2 ALE Psen Power Down and IdleStatus of the External Pins during Idle and Power Down Pcon Power Control Register Smod IDLLocal Serial Channel Local Serial Port Mode ControllerSerial Port Mode Mode Load Sbuf Baud Rates MHZ Timer 1 generated commonly used Baud ratesSmod Reti SINGLE-STEP OperationJNB Kawasaki LSI USA Inc Global Serial Channel Introduction11/IDLE CRC None DC JAM CRCCsma Sdlc 11/IDLEExternal clock Internal clock Control cpu Control dma Raw Receive Raw Transmit Preamble BOF Address Info CRC EOF CSMA/CD OverviewCSMA/CD Frame Format Kawasaki LSI USA, Inc Ver .9 KS152JB2 23 24 Interframe Space CSMA/CD Data Encoding Manchester Encoding BIT TimeCollision Detection Jitter ToleranceUnexpected 1-to-0 Transition Narrow PulsesMissing 0-to-1 Transition Resolution of Collisions GSC InactiveResponse to a Detected Collision What the GSC was doing TfifoAlgorithm BackoffDCR BKOFF= Myslot Random BackoffPrbs Tcdcnt Load Bkoff Slot Clock Myslot Deterministic Backoff Hardware Based Acknowledge Kawasaki LSI USA, Inc Ver .9 KS152JB2 Sdlc Frame Format BOF Address Control Info CRC EOFKawasaki LSI USA, Inc Ver .9 KS152JB2 BIT STUFFING/STRIPPING Data EncodingNrzi BIT Time Acknowledgement Sending Abort CharacterLine Idle PRIMARY/SECONDARY Stations Point-to-point NetworkMulti-Drop Network Ring NetworkUsing a Preamble in Sdlc HDLC/SDLC ComparisonSdlc Hdlc User Defined ProtocolsLine Discipline Planning for Network Changes and ExpansionsDMA Servicing of GSC Channels Kawasaki LSI USA, Inc Ver .9 KS152JB2 Baud Rate Initialization Test Modes External Driver InterfaceJitter Receive Local Value Manchester Encoding BIT Time Receive Sampling Rate ReceivedBIT Time Received Transmit WaveformsReceiver Clock Recovery CSMA/CD Clock RecoveryDetermining Receiver Errors External ClockingRcbat Crce Addressing Determining Line Discipline 2 CPU/DMA Control of the GSCCollisions and Backoff What the GSC was doing Response GSC Register Descriptions Successful Ending of Transmissions and ReceptionsGMOD84H Xtclk PL1 PL0 PL1 PL0 Length BitsKawasaki LSI USA, Inc Ver .9 KS152JB2 DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 ARB REQ Garen Xrclk Gfien IDLRcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc Ver .9 KS152JB2 LNI Noack Tcdt TDN Tfnf TEN DMA Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Operation DMA with the 80C152DMA Registers Alternate Cycle Mode Burst ModeDAS IDA SAS ISASerial Port Demand Mode External Demand ModeTiming Diagrams 12 OSC.PERIODS ALE Psen P1 Inst FloatPCH P2 SFR DMA Cycle Resume Program Execution DMA Transfer from Internal Memory to Internal MemoryDMA Cycle Resume Program Execution 12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCHDMA Cycle 12 OSC. Periods Resume Program Execution ALE Psen Hold/Hold Acknowledge Request ModeArbiter Mode Using the HOLD/HLDA Acknowledge ARB REQDmxrq ALE ARB If Hlda = ALE AEQ ALE REQInternal Logic of the Arbiter Internal Logic of the Requester DMA Arbitration Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Arbitration with Hold/Hold Ack Summary of DMA Control Bits DAS IDA SAS ISA DoneInterrupt Structure IE0 TI+RI ET1 EX1 ET0 EX0PT1 PX1 PT0 PX0 IPN1GSC Transmitter Error Conditions Transmit Error Flags Logic for Clearing TEN, Setting TDNGSC Receiver Error Conditions Glossary Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCON0/1 092H,093H Xtclk PL1 PL0 Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2 PT1 PX1 PT0 EX0 Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Smod ARB REQ Garen Xrclk Gfien IDL OVR Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2 SM0 SM1 SM2 REN TB8 RB8 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0Gate Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2 Port Stack PointerData Pointer LOW DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0Timer Control Data Pointer HighDPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0 DPHTimer Mode Control Gate TimerTimer 0 LSB Timer 1 LSBTimer 0 MSB Timer 1 MSBSerial Port Control SM0Serial Data Buffer SBUF.7Program Status Word RS1 RS0Accumulator ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0Kawasaki LSI USA, Inc 119 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2
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