Kawasaki KS152JB, 80C152, 80C51 Control cpu Control dma Raw Receive Raw Transmit

Page 36

KS152JB Universal Communications Controller Technical Specifications

Table 10:

 

backoff

 

 

preamble

Jam

Clock

contr

 

r

 

 

 

 

 

 

ol

r

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

a

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

a

 

 

 

 

 

 

d

 

 

 

 

 

 

 

 

 

 

 

 

w

c

 

 

 

 

 

 

 

 

 

 

 

 

e

i

 

 

 

w

 

N-Not available.

 

 

 

e

 

 

 

 

 

 

 

 

 

 

 

s

 

 

a

 

 

 

 

 

 

 

 

 

 

 

 

 

s

 

 

t

 

 

 

 

 

 

 

x

n

 

 

 

 

r

m

M-Mandatory.

n

lt

 

e

n

 

8

3

6

 

c

 

 

 

tr

d

O-Optional.

 

 

 

t

t

 

 

 

e

a

o

e

 

r

 

 

2

4

 

c

 

d

a

l

P-Normally Preferred

 

o

 

 

d

r

e

e

 

c

/

r

r

 

m

 

b

 

 

p

 

m

n

c

X-N/A

m

n

 

i

n

 

 

 

c

c

r

r

 

e

c

 

 

i

b

b

u

 

a

s

 

 

a

a

 

n

e

 

 

/

n

n

 

i

d

 

 

l

t

 

i

 

t

it

it

 

 

 

 

m

 

 

 

 

 

 

 

a

a

 

 

 

v

 

 

 

 

e

 

s

 

 

 

 

 

 

 

 

 

 

it

 

 

 

 

 

 

ti

 

 

 

 

 

 

 

l

l

 

 

 

e

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

c

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Control cpu

O

O

 

O

O

 

O

O

O

O

O

O

O

X

 

N

O

O

O

O

Control dma

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

O

O

O

 

O

O

O

O

O

O

O

N

X

O

O

O

O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Raw Receive

O

O

 

O

1

 

1

1

1

O

O

1

1

1

 

1

X

N

1

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Raw Transmit

N

N

 

N

1

 

1

1

1

N

N

1

1

1

 

1

N

X

1

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CSMA

O

O

 

O

N

 

O

O

O

O

O

N

O

O

 

O

O

O

X

N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SDLC

N

N

 

N

P

 

O

O

O

N

N

O

O

O

 

O

O

O

N

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note 1: Programmable in Raw transmit or receive mode.

Almost all the options available from Table can be implemented with the proper software to per- form the functions that are necessary for the options selected. In Table 3.1, a judgment has been made by the authors on which options are practical and which are not. What this means is that in table , an “N” should be interpreted as meaning that the option is either not practical when imple- mented with user software or that it cannot be done. An “O” is used when that function is one of several that can be implement with the GSC without additional user software.

The GSC is targeted to operate at bit rates up to 2.4 Mbps using the external clock options and up to 2 MBps using the internal baud rate generator, internal data formatting and on-chip clock recovery. The baud rate generator allows most standard rates to be achieved. These standards include the proposed IEEE802.3 LAN standard(1.0MBps) and the T1 standard (1.544Mbps). The baud rate is derived from the crystal frequency. This makes crystal selection important when determining the frequency and accuracy of the baud rate.

The user needs to be aware that after reset, the GSC is in CSMA/CD mode, IFS = 256 bit times, and a bit time equals 8 oscillator periods. The GSC will remain in this mode until the interframe space expires. If the user changes to SDLC mode or the parameters used in CSMA/CD, these changes will not take effect until the interframe space expires. A requirement for the interframe space timer to begin is that the receiver be in an idle state. This makes it possible for the GSC to

Kawasaki LSI USA, Inc.

Page 36 of 120

Ver. 0.9 KS152JB2

Image 36
Contents Introduction Technical Specifications Pin Description PIN DescriptionName Description Port Pin Name Alternate FunctionXTAL1 XTAL2RST ALE PsenEben EpsenSpecial function Registers SFR map for the cpuReset Timing Reset Values of the SFRs Configurations SconSbuf Indeterminate Tmod PconPort 0 I/O Pad Port 2 I/O Pad Port bit I/O PadsPorts 4,5 Program Psen EpsenComments Fetch viaTIMER/COUNTERS Tmod Timer/Counter Mode Control RegisterTcon Timer/Counter Control Register ModeTimer/Counter in Mode Timer/Counter 0 in Mode IE Interrupt Enable RegisterInterrupts Priority Level Structure Egste EDMA1 Egstv EDMA0 Egsre Egsrv Pgste PDMA1 Pgstv PDMA0 Pgsre PgsrvPX0 EX0Pgsrv Egsrv 2BHPDMA1 EDMA1PT1 ET1 1BHKawasaki LSI USA, Inc Ver .9 KS152JB2 Power Down and Idle Status of the External Pins during Idle and Power DownALE Psen Pcon Power Control Register Smod IDLLocal Serial Channel Local Serial Port Mode ControllerSerial Port Mode Mode Load Sbuf Baud Rates Timer 1 generated commonly used Baud rates SmodMHZ SINGLE-STEP Operation JNBReti Kawasaki LSI USA Inc Global Serial Channel Introduction 11/IDLE CRC None DC JAM CRCCsma Sdlc 11/IDLEExternal clock Internal clock Control cpu Control dma Raw Receive Raw Transmit CSMA/CD Overview CSMA/CD Frame FormatPreamble BOF Address Info CRC EOF Kawasaki LSI USA, Inc Ver .9 KS152JB2 23 24 Interframe Space CSMA/CD Data Encoding Manchester Encoding BIT TimeCollision Detection Jitter ToleranceNarrow Pulses Missing 0-to-1 TransitionUnexpected 1-to-0 Transition Resolution of Collisions GSC InactiveResponse to a Detected Collision What the GSC was doing TfifoBackoff DCRAlgorithm Random Backoff Prbs Tcdcnt Load Bkoff Slot Clock MyslotBKOFF= Myslot Deterministic Backoff Hardware Based Acknowledge Kawasaki LSI USA, Inc Ver .9 KS152JB2 Sdlc Frame Format BOF Address Control Info CRC EOFKawasaki LSI USA, Inc Ver .9 KS152JB2 Data Encoding Nrzi BIT TimeBIT STUFFING/STRIPPING Sending Abort Character Line IdleAcknowledgement PRIMARY/SECONDARY Stations Point-to-point NetworkMulti-Drop Network Ring NetworkUsing a Preamble in Sdlc HDLC/SDLC ComparisonSdlc Hdlc User Defined ProtocolsLine Discipline Planning for Network Changes and ExpansionsDMA Servicing of GSC Channels Kawasaki LSI USA, Inc Ver .9 KS152JB2 Baud Rate Initialization Test Modes External Driver InterfaceJitter Receive Local Value Manchester Encoding BIT Time Receive Sampling Rate ReceivedBIT Time Received Transmit WaveformsReceiver Clock Recovery CSMA/CD Clock RecoveryDetermining Receiver Errors External ClockingRcbat Crce AddressingDetermining Line Discipline 2 CPU/DMA Control of the GSCCollisions and Backoff What the GSC was doing Response GSC Register Descriptions Successful Ending of Transmissions and ReceptionsGMOD84H Xtclk PL1 PL0 PL1 PL0 Length BitsKawasaki LSI USA, Inc Ver .9 KS152JB2 DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 ARB REQ Garen Xrclk Gfien IDLRcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc Ver .9 KS152JB2 LNI Noack Tcdt TDN Tfnf TEN DMA Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Operation DMA with the 80C152DMA Registers Alternate Cycle Mode Burst ModeDAS IDA SAS ISASerial Port Demand Mode External Demand ModeTiming Diagrams 12 OSC.PERIODS ALE Psen P1 Inst FloatPCH P2 SFR DMA Cycle Resume Program Execution DMA Transfer from Internal Memory to Internal Memory12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCH DMA Cycle 12 OSC. Periods Resume Program Execution ALE PsenDMA Cycle Resume Program Execution Request Mode Arbiter ModeHold/Hold Acknowledge Using the HOLD/HLDA Acknowledge ARB REQALE ARB If Hlda = ALE AEQ ALE REQ Internal Logic of the ArbiterDmxrq Internal Logic of the Requester DMA Arbitration Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Arbitration with Hold/Hold Ack Summary of DMA Control Bits DAS IDA SAS ISA DoneInterrupt Structure IE0 TI+RI ET1 EX1 ET0 EX0PT1 PX1 PT0 PX0 IPN1GSC Transmitter Error Conditions Transmit Error Flags Logic for Clearing TEN, Setting TDNGSC Receiver Error Conditions Glossary Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCON0/1 092H,093H Xtclk PL1 PL0 Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2 PT1 PX1 PT0 EX0 Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Smod ARB REQ Garen Xrclk Gfien IDL OVR Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2 SM0 SM1 SM2 REN TB8 RB8 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0Gate Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2 Port Stack PointerData Pointer LOW DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0Timer Control Data Pointer HighDPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0 DPHTimer Mode Control Gate TimerTimer 0 LSB Timer 1 LSBTimer 0 MSB Timer 1 MSBSerial Port Control SM0Serial Data Buffer SBUF.7Program Status Word RS1 RS0Accumulator ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0Kawasaki LSI USA, Inc 119 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2