Kawasaki 80C51, KS152JB, 80C152 technical specifications External clock Internal clock

Page 35

KS152JB Universal Communications Controller Technical Specifications

Table 10:

 

 

 

backoff

 

 

preamble

Jam

Clock

contr

 

r

 

 

 

 

 

 

 

 

ol

r

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

a

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

a

 

 

 

 

 

 

 

 

d

 

 

 

 

 

 

 

 

 

 

 

 

w

c

 

 

 

 

 

 

 

 

 

 

 

 

 

 

e

i

 

 

 

w

 

 

N-Not available.

 

 

 

e

 

 

 

 

 

 

 

 

 

 

 

s

 

 

 

a

 

 

 

 

 

 

 

 

 

 

 

 

 

s

 

 

 

t

 

 

 

 

 

 

 

x

n

 

 

 

 

r

m

 

 

M-Mandatory.

n

lt

 

e

n

 

8

3

6

 

c

 

 

 

tr

d

 

 

O-Optional.

 

 

 

t

t

 

 

 

e

a

 

 

o

e

 

r

 

 

2

4

 

c

 

d

a

l

 

P-Normally Preferred

 

o

 

 

d

r

e

e

 

c

/

 

r

r

 

m

 

b

 

 

p

 

m

n

c

 

 

X-N/A

m

n

 

i

n

 

 

 

c

c

r

r

 

e

c

 

 

 

 

i

b

b

u

 

a

s

 

 

 

 

a

a

 

n

e

 

 

/

n

n

 

i

d

 

 

 

 

l

t

 

i

 

t

it

it

 

 

 

 

m

 

 

 

 

 

 

 

 

 

a

a

 

 

 

v

 

 

 

 

 

 

e

 

s

 

 

 

 

 

 

 

 

 

 

it

 

 

 

 

 

 

 

 

ti

 

 

 

 

 

 

 

l

l

 

 

 

e

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

c

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CRC: NONE

N

N

 

N

1

 

1

1

1

N

N

1

1

1

 

1

1

1

1

1

 

16-bit CCITT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

O

O

O

 

O

O

O

O

O

O

O

O

 

O

1

1

O

O

 

32-bitAUTODIN II

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

O

O

O

 

O

O

O

O

O

O

O

O

 

O

1

1

O

O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Half Duples

O

O

 

O

O

 

O

O

O

O

O

O

O

O

 

O

O

O

O

O

 

Full Duplex

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

N

N

N

O

 

O

O

O

N

N

O

O

O

 

O

N

N

N

P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Acknowledge: None

O

O

 

O

O

 

O

O

O

O

O

O

O

O

 

O

O

O

O

O

 

Hardware

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

N

O

O

N

 

O

O

O

O

O

N

O

O

 

O

N

N

O

N

 

User defined.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

O

O

O

 

O

O

O

O

O

O

O

O

 

O

O

O

O

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address recog: none

O

O

 

O

O

 

O

O

O

O

O

O

O

O

 

O

O

O

O

O

 

8-bit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

O

O

O

 

O

O

O

O

O

O

O

O

 

O

1

1

O

O

 

16 bit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

O

O

O

 

O

O

O

O

O

O

O

O

 

O

1

1

O

O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Coll resol: Normal

X

N

 

N

N

 

O

O

O

O

O

N

O

O

 

O

O

N

M

N

 

Alternate

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

N

X

N

N

 

O

O

O

O

O

N

O

O

 

O

O

N

M

N

 

Deterministic

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

N

N

X

N

 

O

O

O

O

O

N

O

O

 

O

O

N

M

N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Preamble: None

N

N

 

N

X

 

N

N

N

N

N

O

O

O

 

O

O

O

N

P

 

8-bit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

O

 

O

N

 

X

N

N

O

O

O

O

O

 

O

1

1

O

O

 

32-bit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

O

O

N

 

N

X

N

O

O

O

O

O

 

O

1

1

O

O

 

64-bit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

O

O

N

 

N

N

X

O

O

O

O

O

 

O

N

N

O

O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DC JAM

O

O

 

O

N

 

O

O

O

X

N

N

O

O

 

O

O

N

M

N

 

 

JAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CRC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

O

O

N

 

O

O

O

N

X

N

O

O

 

O

O

N

M

N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

External clock

N

N

 

N

O

 

O

O

O

N

N

X

N

O

 

O

O

O

N

O

 

Internal clock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

O

O

O

 

O

O

O

O

O

N

X

O

 

O

O

O

O

O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Kawasaki LSI USA, Inc.

Page 35 of 120

Ver. 0.9 KS152JB2

Page 34 Page 36
Image 35
Page 34 Page 36
Contents Introduction Technical Specifications Pin Name Alternate Function Pin DescriptionPIN Description Name Description PortRST XTAL1XTAL2 Epsen ALEPsen EbenSFR map for the cpu Special function RegistersReset Timing Reset Values of the SFRs Pcon ConfigurationsScon Sbuf Indeterminate TmodPort bit I/O Pads Port 0 I/O Pad Port 2 I/O PadPorts 4,5 Fetch via ProgramPsen Epsen CommentsTmod Timer/Counter Mode Control Register TIMER/COUNTERSMode Tcon Timer/Counter Control RegisterTimer/Counter in Mode Interrupts Timer/Counter 0 in ModeIE Interrupt Enable Register Priority Level Structure Pgste PDMA1 Pgstv PDMA0 Pgsre Pgsrv Egste EDMA1 Egstv EDMA0 Egsre EgsrvEgsrv 2BH PX0EX0 PgsrvET1 1BH PDMA1EDMA1 PT1Kawasaki LSI USA, Inc Ver .9 KS152JB2 ALE Psen Power Down and IdleStatus of the External Pins during Idle and Power Down Smod IDL Pcon Power Control RegisterLocal Serial Channel Controller Local Serial Port ModeSerial Port Mode Mode Load Sbuf Baud Rates MHZ Timer 1 generated commonly used Baud ratesSmod Reti SINGLE-STEP OperationJNB Kawasaki LSI USA Inc Introduction Global Serial ChannelDC JAM CRC 11/IDLE CRC None11/IDLE Csma SdlcExternal clock Internal clock Control cpu Control dma Raw Receive Raw Transmit Preamble BOF Address Info CRC EOF CSMA/CD OverviewCSMA/CD Frame Format Kawasaki LSI USA, Inc Ver .9 KS152JB2 23 24 Interframe Space Jitter Tolerance CSMA/CD Data EncodingManchester Encoding BIT Time Collision DetectionUnexpected 1-to-0 Transition Narrow PulsesMissing 0-to-1 Transition Tfifo Resolution of CollisionsGSC Inactive Response to a Detected Collision What the GSC was doingAlgorithm BackoffDCR BKOFF= Myslot Random BackoffPrbs Tcdcnt Load Bkoff Slot Clock Myslot Deterministic Backoff Hardware Based Acknowledge Kawasaki LSI USA, Inc Ver .9 KS152JB2 BOF Address Control Info CRC EOF Sdlc Frame FormatKawasaki LSI USA, Inc Ver .9 KS152JB2 BIT STUFFING/STRIPPING Data EncodingNrzi BIT Time Acknowledgement Sending Abort CharacterLine Idle Ring Network PRIMARY/SECONDARY StationsPoint-to-point Network Multi-Drop NetworkUser Defined Protocols Using a Preamble in SdlcHDLC/SDLC Comparison Sdlc HdlcPlanning for Network Changes and Expansions Line DisciplineDMA Servicing of GSC Channels Kawasaki LSI USA, Inc Ver .9 KS152JB2 Baud Rate Initialization External Driver Interface Test ModesJitter Receive Transmit Waveforms Local Value Manchester Encoding BIT TimeReceive Sampling Rate Received BIT Time ReceivedCSMA/CD Clock Recovery Receiver Clock RecoveryAddressing Determining Receiver ErrorsExternal Clocking Rcbat Crce2 CPU/DMA Control of the GSC Determining Line DisciplineCollisions and Backoff What the GSC was doing Response Successful Ending of Transmissions and Receptions GSC Register DescriptionsPL1 PL0 Length Bits GMOD84H Xtclk PL1 PL0Kawasaki LSI USA, Inc Ver .9 KS152JB2 ARB REQ Garen Xrclk Gfien IDL DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc Ver .9 KS152JB2 LNI Noack Tcdt TDN Tfnf TEN DMA Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA with the 80C152 DMA OperationDMA Registers SAS ISA Alternate Cycle ModeBurst Mode DAS IDAExternal Demand Mode Serial Port Demand ModeDMA Transfer from Internal Memory to Internal Memory Timing Diagrams12 OSC.PERIODS ALE Psen P1 Inst Float PCH P2 SFR DMA Cycle Resume Program ExecutionDMA Cycle Resume Program Execution 12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCHDMA Cycle 12 OSC. Periods Resume Program Execution ALE Psen Hold/Hold Acknowledge Request ModeArbiter Mode ARB REQ Using the HOLD/HLDA AcknowledgeDmxrq ALE ARB If Hlda = ALE AEQ ALE REQInternal Logic of the Arbiter Internal Logic of the Requester DMA Arbitration Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Arbitration with Hold/Hold Ack DAS IDA SAS ISA Done Summary of DMA Control BitsInterrupt Structure IE0 ET1 EX1 ET0 EX0 TI+RIIPN1 PT1 PX1 PT0 PX0Transmit Error Flags Logic for Clearing TEN, Setting TDN GSC Transmitter Error ConditionsGSC Receiver Error Conditions Glossary Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCON0/1 092H,093H Xtclk PL1 PL0 Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2 PT1 PX1 PT0 EX0 Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Smod ARB REQ Garen Xrclk Gfien IDL OVR Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 SM0 SM1 SM2 REN TB8 RB8Gate Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2 DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0 PortStack Pointer Data Pointer LOWDPH Timer ControlData Pointer High DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0Timer 1 LSB Timer Mode ControlGate Timer Timer 0 LSBTimer 1 MSB Timer 0 MSBSBUF.7 Serial Port ControlSM0 Serial Data BufferRS1 RS0 Program Status WordACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 AccumulatorKawasaki LSI USA, Inc 119 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2
Top Page Image Contents