Kawasaki 80C152, KS152JB, 80C51 Line Discipline, Planning for Network Changes and Expansions

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KS152JB Universal Communications Controller Technical Specifications

3.5 USING THE GSC

3.5.1 LINE DISCIPLINE

Line discipline is how the management of the transfer of data over the physical medium is con- trolled. Two types of line discipline will be discussed in this section: full duplex and half duplex.

Full duplex is the simultaneous transmission and reception of data.Full duplex uses anywhere from two to four wires. At least one wire is needed for transmission and one write for reception. Usually there will also be a ground reference on each signal if the distance from station to station is relatively long. Full-duplex operation in the dC152 requires that both the receive and the trans- mit portion of the GSC are functioning at the same time. Since both the transmitter and receiver are operating, two CRC generators are also needed. The C152 handles this problem by having one 32-bit CRC generator and one 16-bit CRC generator. When supporting full-duplex operation, the 32-bit CRC generator is modified to work as a 16-bit CRC generator. When ever the 16-bit CRC is selected, the GSC automatically enters the full duplex mode. Half duplex with a 16-bit CRC is discussed in the following paragraph.

Half duplex is the alternate transmission and reception of data over a single common wire. Only one or two wires are needed in half-duplex systems. One wire is needed for the signal and if the distance to be covered is long there will also be a wire for the found reference. In half-duplex mode, only the receiver or transmitter can operate at one time. When the receiver or transmitter operates is determined by user software, but typically the receiver will always be enabled unless the GSC is transmitting. When using the C152 in half-duplex and the receiver is connected to the transmitter it is possible that a station will receive its’ own transmission. This can occur if a broadcast address is sent, the address mask register(s) are filled with all 1s, or the address being sent matches the sending stations address through the use of the address masking registers. the receiver must be disabled by the user while transmitting if any of these conditions will occur, unless the user wants a station to receive its own transmission. The receiver is disabled by clearing GREN (and GAREN if used). Half-duplex operation in the C152 is supported with either 16-bit or 32-bit CRCs. Whenever a 32-bit CRC is selected, only half-duplex operation can be supported by the GSC. It is possible to simulate full-duplex operation with a 32-bit CRC, but this would require that the CRC be performed with software. Calculating the CRC with the CPU would greatly reduce the data rates that could be used with the GSC. Whenever a 16-bit CRC is selected, full- duplex operation is automatically chosen and the GSC must be reconfigured if half duplex opera- tion is preferred.

3.5.2 PLANNING FOR NETWORK CHANGES AND EXPANSIONS

A complete explanation on ho to plan for network expansion will not be covered in this manual as there are far too many possibilities that would need to be discussed. But there are several areas that will have major impact when allowing for changes in the system. In cases where there will never be any changes allowed, expansion plans become a mute issue. However, it is strongly sug- gested that there always be some allowance for future modifications.

Kawasaki LSI USA, Inc.

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Ver. 0.9 KS152JB2

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Contents Introduction Technical Specifications Pin Name Alternate Function Pin DescriptionPIN Description Name Description PortXTAL2 XTAL1RST Epsen ALEPsen EbenSFR map for the cpu Special function RegistersReset Timing Reset Values of the SFRs Pcon ConfigurationsScon Sbuf Indeterminate TmodPort bit I/O Pads Port 0 I/O Pad Port 2 I/O PadPorts 4,5 Fetch via ProgramPsen Epsen CommentsTmod Timer/Counter Mode Control Register TIMER/COUNTERSMode Tcon Timer/Counter Control RegisterTimer/Counter in Mode IE Interrupt Enable Register Timer/Counter 0 in ModeInterrupts Priority Level Structure Pgste PDMA1 Pgstv PDMA0 Pgsre Pgsrv Egste EDMA1 Egstv EDMA0 Egsre EgsrvEgsrv 2BH PX0EX0 PgsrvET1 1BH PDMA1EDMA1 PT1Kawasaki LSI USA, Inc Ver .9 KS152JB2 Status of the External Pins during Idle and Power Down Power Down and IdleALE Psen Smod IDL Pcon Power Control RegisterLocal Serial Channel Controller Local Serial Port ModeSerial Port Mode Mode Load Sbuf Baud Rates Smod Timer 1 generated commonly used Baud ratesMHZ JNB SINGLE-STEP OperationReti Kawasaki LSI USA Inc Introduction Global Serial ChannelDC JAM CRC 11/IDLE CRC None11/IDLE Csma SdlcExternal clock Internal clock Control cpu Control dma Raw Receive Raw Transmit CSMA/CD Frame Format CSMA/CD OverviewPreamble BOF Address Info CRC EOF Kawasaki LSI USA, Inc Ver .9 KS152JB2 23 24 Interframe Space Jitter Tolerance CSMA/CD Data EncodingManchester Encoding BIT Time Collision DetectionMissing 0-to-1 Transition Narrow PulsesUnexpected 1-to-0 Transition Tfifo Resolution of CollisionsGSC Inactive Response to a Detected Collision What the GSC was doingDCR BackoffAlgorithm Prbs Tcdcnt Load Bkoff Slot Clock Myslot Random BackoffBKOFF= Myslot Deterministic Backoff Hardware Based Acknowledge Kawasaki LSI USA, Inc Ver .9 KS152JB2 BOF Address Control Info CRC EOF Sdlc Frame FormatKawasaki LSI USA, Inc Ver .9 KS152JB2 Nrzi BIT Time Data EncodingBIT STUFFING/STRIPPING Line Idle Sending Abort CharacterAcknowledgement Ring Network PRIMARY/SECONDARY StationsPoint-to-point Network Multi-Drop NetworkUser Defined Protocols Using a Preamble in SdlcHDLC/SDLC Comparison Sdlc HdlcPlanning for Network Changes and Expansions Line DisciplineDMA Servicing of GSC Channels Kawasaki LSI USA, Inc Ver .9 KS152JB2 Baud Rate Initialization External Driver Interface Test ModesJitter Receive Transmit Waveforms Local Value Manchester Encoding BIT TimeReceive Sampling Rate Received BIT Time ReceivedCSMA/CD Clock Recovery Receiver Clock RecoveryAddressing Determining Receiver ErrorsExternal Clocking Rcbat Crce2 CPU/DMA Control of the GSC Determining Line DisciplineCollisions and Backoff What the GSC was doing Response Successful Ending of Transmissions and Receptions GSC Register DescriptionsPL1 PL0 Length Bits GMOD84H Xtclk PL1 PL0Kawasaki LSI USA, Inc Ver .9 KS152JB2 ARB REQ Garen Xrclk Gfien IDL DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc Ver .9 KS152JB2 LNI Noack Tcdt TDN Tfnf TEN DMA Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA with the 80C152 DMA OperationDMA Registers SAS ISA Alternate Cycle ModeBurst Mode DAS IDAExternal Demand Mode Serial Port Demand ModeDMA Transfer from Internal Memory to Internal Memory Timing Diagrams12 OSC.PERIODS ALE Psen P1 Inst Float PCH P2 SFR DMA Cycle Resume Program ExecutionDMA Cycle 12 OSC. Periods Resume Program Execution ALE Psen 12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCHDMA Cycle Resume Program Execution Arbiter Mode Request ModeHold/Hold Acknowledge ARB REQ Using the HOLD/HLDA AcknowledgeInternal Logic of the Arbiter ALE ARB If Hlda = ALE AEQ ALE REQDmxrq Internal Logic of the Requester DMA Arbitration Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Arbitration with Hold/Hold Ack DAS IDA SAS ISA Done Summary of DMA Control BitsInterrupt Structure IE0 ET1 EX1 ET0 EX0 TI+RIIPN1 PT1 PX1 PT0 PX0Transmit Error Flags Logic for Clearing TEN, Setting TDN GSC Transmitter Error ConditionsGSC Receiver Error Conditions Glossary Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCON0/1 092H,093H Xtclk PL1 PL0 Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2 PT1 PX1 PT0 EX0 Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Smod ARB REQ Garen Xrclk Gfien IDL OVR Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 SM0 SM1 SM2 REN TB8 RB8Gate Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2 DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0 PortStack Pointer Data Pointer LOWDPH Timer ControlData Pointer High DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0Timer 1 LSB Timer Mode ControlGate Timer Timer 0 LSBTimer 1 MSB Timer 0 MSBSBUF.7 Serial Port ControlSM0 Serial Data BufferRS1 RS0 Program Status WordACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 AccumulatorKawasaki LSI USA, Inc 119 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2
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