Kawasaki KS152JB, 80C152, 80C51 technical specifications GSC Transmitter Error Conditions

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KS152JB Universal Communications Controller Technical Specifications

It is recommended that user software should never write 1s to unimplemented bits in MCS-51 devices. Further versions of the device may have new bits installed in these locations. If so, their reset value will be 0. Old software that writes 1s to newly implemented bits may unexpectedly invoke new features.

The MCS-51 interrupt structure provides hardware support for only two priority levels, High and Low. With as many interrupt sources as the 8XC152 has, it may be helpful to know how to aug- ment the priority structure in the software. Any number of priority levels can be implemented in software by saving and redeﬁning the interrupt enable registers within the interrupt service rou- tines.

5.1 GSC Transmitter Error Conditions

The GSC Transmitter section reports three kinds of error conditions:

TCDT - Transmitter Collision Detector

UR - Underrun in Transmit FIFO

NOACK - No Acknowledge

These bits reside in the TSTAT register. User software can read them, but only the GSC hardware can write to them. The GSC hardware will set them in response to the various error conditions that they represent. When the user software sets the TEN bit, the GSC hardware will at that time clear these ﬂags. This is the only way these ﬂags can be cleared.

The logical OR of these three bits ﬂags the GSC Transmit Error interrupt (GSCTE) and clears the TEN bit, as shown in Figure below. Thus any detected error condition aborts the transmission. No CRC bits are transmitted. In the SDLC mode an EOF is generated. In CSMA/CD mode an EOF is generated by default, since the GTXD pin is pulled to a logic 1 and held there.

TCDT

UR

NOACK

TEN

TRANSMIT EOF

GSCTE

Clear

TEN

Set

TDN

Transmit Error Flags (Logic for Clearing TEN, Setting TDN)

The TCDT bit can get set only if the GSC is conﬁgured to CSMA/CD mode. In that case the GSC hardware sets the TCDT when a collision is detected during a transmission, and the collision was detected after TFIFO has been accessed. Also, the GSC hardware sets TCDT when a detected col- lision causes the TCDCNT register to overﬂow.

Kawasaki LSI USA, Inc.

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Ver. 0.9 KS152JB2

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Contents Introduction Technical Specifications Pin Description PIN DescriptionName Description Port Pin Name Alternate FunctionXTAL1 XTAL2RST ALE PsenEben EpsenSpecial function Registers SFR map for the cpuReset Timing Reset Values of the SFRs Configurations SconSbuf Indeterminate Tmod PconPort 0 I/O Pad Port 2 I/O Pad Port bit I/O PadsPorts 4,5 Program Psen EpsenComments Fetch viaTIMER/COUNTERS Tmod Timer/Counter Mode Control RegisterTcon Timer/Counter Control Register ModeTimer/Counter in Mode Timer/Counter 0 in Mode IE Interrupt Enable RegisterInterrupts Priority Level Structure Egste EDMA1 Egstv EDMA0 Egsre Egsrv Pgste PDMA1 Pgstv PDMA0 Pgsre PgsrvPX0 EX0Pgsrv Egsrv 2BHPDMA1 EDMA1PT1 ET1 1BHKawasaki LSI USA, Inc Ver .9 KS152JB2 Power Down and Idle Status of the External Pins during Idle and Power DownALE Psen Pcon Power Control Register Smod IDLLocal Serial Channel Local Serial Port Mode ControllerSerial Port Mode Mode Load Sbuf Baud Rates Timer 1 generated commonly used Baud rates SmodMHZ SINGLE-STEP Operation JNBReti Kawasaki LSI USA Inc Global Serial Channel Introduction11/IDLE CRC None DC JAM CRCCsma Sdlc 11/IDLEExternal clock Internal clock Control cpu Control dma Raw Receive Raw Transmit CSMA/CD Overview CSMA/CD Frame FormatPreamble BOF Address Info CRC EOF Kawasaki LSI USA, Inc Ver .9 KS152JB2 23 24 Interframe Space CSMA/CD Data Encoding Manchester Encoding BIT TimeCollision Detection Jitter ToleranceNarrow Pulses Missing 0-to-1 TransitionUnexpected 1-to-0 Transition Resolution of Collisions GSC InactiveResponse to a Detected Collision What the GSC was doing TfifoBackoff DCRAlgorithm Random Backoff Prbs Tcdcnt Load Bkoff Slot Clock MyslotBKOFF= Myslot Deterministic Backoff Hardware Based Acknowledge Kawasaki LSI USA, Inc Ver .9 KS152JB2 Sdlc Frame Format BOF Address Control Info CRC EOFKawasaki LSI USA, Inc Ver .9 KS152JB2 Data Encoding Nrzi BIT TimeBIT STUFFING/STRIPPING Sending Abort Character Line IdleAcknowledgement PRIMARY/SECONDARY Stations Point-to-point NetworkMulti-Drop Network Ring NetworkUsing a Preamble in Sdlc HDLC/SDLC ComparisonSdlc Hdlc User Deﬁned ProtocolsLine Discipline Planning for Network Changes and ExpansionsDMA Servicing of GSC Channels Kawasaki LSI USA, Inc Ver .9 KS152JB2 Baud Rate Initialization Test Modes External Driver InterfaceJitter Receive Local Value Manchester Encoding BIT Time Receive Sampling Rate ReceivedBIT Time Received Transmit WaveformsReceiver Clock Recovery CSMA/CD Clock RecoveryDetermining Receiver Errors External ClockingRcbat Crce AddressingDetermining Line Discipline 2 CPU/DMA Control of the GSCCollisions and Backoff What the GSC was doing Response GSC Register Descriptions Successful Ending of Transmissions and ReceptionsGMOD84H Xtclk PL1 PL0 PL1 PL0 Length BitsKawasaki LSI USA, Inc Ver .9 KS152JB2 DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 ARB REQ Garen Xrclk Gfien IDLRcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc Ver .9 KS152JB2 LNI Noack Tcdt TDN Tfnf TEN DMA Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Operation DMA with the 80C152DMA Registers Alternate Cycle Mode Burst ModeDAS IDA SAS ISASerial Port Demand Mode External Demand ModeTiming Diagrams 12 OSC.PERIODS ALE Psen P1 Inst FloatPCH P2 SFR DMA Cycle Resume Program Execution DMA Transfer from Internal Memory to Internal Memory12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCH DMA Cycle 12 OSC. Periods Resume Program Execution ALE PsenDMA Cycle Resume Program Execution Request Mode Arbiter ModeHold/Hold Acknowledge Using the HOLD/HLDA Acknowledge ARB REQALE ARB If Hlda = ALE AEQ ALE REQ Internal Logic of the ArbiterDmxrq Internal Logic of the Requester DMA Arbitration Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Arbitration with Hold/Hold Ack Summary of DMA Control Bits DAS IDA SAS ISA DoneInterrupt Structure IE0 TI+RI ET1 EX1 ET0 EX0PT1 PX1 PT0 PX0 IPN1GSC Transmitter Error Conditions Transmit Error Flags Logic for Clearing TEN, Setting TDNGSC Receiver Error Conditions Glossary Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCON0/1 092H,093H Xtclk PL1 PL0 Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2 PT1 PX1 PT0 EX0 Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Smod ARB REQ Garen Xrclk Gfien IDL OVR Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2 SM0 SM1 SM2 REN TB8 RB8 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0Gate Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2 Port Stack PointerData Pointer LOW DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0Timer Control Data Pointer HighDPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0 DPHTimer Mode Control Gate TimerTimer 0 LSB Timer 1 LSBTimer 0 MSB Timer 1 MSBSerial Port Control SM0Serial Data Buffer SBUF.7Program Status Word RS1 RS0Accumulator ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0Kawasaki LSI USA, Inc 119 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2