Kawasaki 80C51 Scon, Sbuf Indeterminate Tmod, Pcon, Tcon, DARL0-1 Indeterminate DCON0-1, Gmod

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KS152JB Universal Communications Controller Technical Specifications

Table 3: Reset Values of the SFRs

SFR Name	Reset Value	SFR Name	Reset Value


IP	XXX00000B	SCON	00H

IE	0XX00000B	SBUF	INDETERMINATE

TMOD	00H	PCON	0XXX0000B

TCON	00H	DARL0-1	INDETERMINATE

DCON0-1	00H	DARh0-1	INDETERMINATE

GMOD	X0000000B	IFS	00H

IEN1	XX000000B	MYSLOT	00H

IPN1	XX000000B	PRBS	00H

TCDCNT	INDETERMINATE	TCON	00H

TFIFO	INDETERMINATE	TSTAT	XX000100B

2.4 PORT STRUCTURES AND OPERATION

The ports are all bidirectional. Each port consists of two sections, the port SFR and the I/O pad.

The Ports 0 and 2 are involved in accesses to external memory. In this case, Port 0 outputs the lower byte of the external memory address while port 2 outputs the higher byte of the external address. The Port 0 bus is also used as a data bus for the data byte that is read or is to be written. Therefore Port 0 is actually a time-multiplexed address/data bus. A point to note is that Port 2 out- puts the upper 8 bits of the address only if the address is 16 bits wide, else it continues to emit the Port 2 SFR contents.

In order that the alternate functions on the port pin are activated correctly, the corresponding bit latch must be held at value 1. If this is not done then the corresponding port pin is stuck at 0, and external or internal inputs will have no effect on the pin value.

I/O CONFIGURATIONS

Each individual port has different I/O pads to accommodate the different functions of each indi- vidual port. The ﬁgure below shows a simpliﬁed diagram of the I/O pads for each port.

Kawasaki LSI USA, Inc.

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Ver. 0.9 KS152JB2

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Contents Introduction Technical Specifications Pin Description PIN DescriptionName Description Port Pin Name Alternate FunctionRST XTAL1XTAL2 ALE PsenEben EpsenSpecial function Registers SFR map for the cpuReset Timing Reset Values of the SFRs Configurations SconSbuf Indeterminate Tmod PconPort 0 I/O Pad Port 2 I/O Pad Port bit I/O PadsPorts 4,5 Program Psen EpsenComments Fetch viaTIMER/COUNTERS Tmod Timer/Counter Mode Control RegisterTcon Timer/Counter Control Register ModeTimer/Counter in Mode Interrupts Timer/Counter 0 in ModeIE Interrupt Enable Register Priority Level Structure Egste EDMA1 Egstv EDMA0 Egsre Egsrv Pgste PDMA1 Pgstv PDMA0 Pgsre PgsrvPX0 EX0Pgsrv Egsrv 2BHPDMA1 EDMA1PT1 ET1 1BHKawasaki LSI USA, Inc Ver .9 KS152JB2 ALE Psen Power Down and IdleStatus of the External Pins during Idle and Power Down Pcon Power Control Register Smod IDLLocal Serial Channel Local Serial Port Mode ControllerSerial Port Mode Mode Load Sbuf Baud Rates MHZ Timer 1 generated commonly used Baud ratesSmod Reti SINGLE-STEP OperationJNB Kawasaki LSI USA Inc Global Serial Channel Introduction11/IDLE CRC None DC JAM CRCCsma Sdlc 11/IDLEExternal clock Internal clock Control cpu Control dma Raw Receive Raw Transmit Preamble BOF Address Info CRC EOF CSMA/CD OverviewCSMA/CD Frame Format Kawasaki LSI USA, Inc Ver .9 KS152JB2 23 24 Interframe Space CSMA/CD Data Encoding Manchester Encoding BIT TimeCollision Detection Jitter ToleranceUnexpected 1-to-0 Transition Narrow PulsesMissing 0-to-1 Transition Resolution of Collisions GSC InactiveResponse to a Detected Collision What the GSC was doing TfifoAlgorithm BackoffDCR BKOFF= Myslot Random BackoffPrbs Tcdcnt Load Bkoff Slot Clock Myslot Deterministic Backoff Hardware Based Acknowledge Kawasaki LSI USA, Inc Ver .9 KS152JB2 Sdlc Frame Format BOF Address Control Info CRC EOFKawasaki LSI USA, Inc Ver .9 KS152JB2 BIT STUFFING/STRIPPING Data EncodingNrzi BIT Time Acknowledgement Sending Abort CharacterLine Idle PRIMARY/SECONDARY Stations Point-to-point NetworkMulti-Drop Network Ring NetworkUsing a Preamble in Sdlc HDLC/SDLC ComparisonSdlc Hdlc User Deﬁned ProtocolsLine Discipline Planning for Network Changes and ExpansionsDMA Servicing of GSC Channels Kawasaki LSI USA, Inc Ver .9 KS152JB2 Baud Rate Initialization Test Modes External Driver InterfaceJitter Receive Local Value Manchester Encoding BIT Time Receive Sampling Rate ReceivedBIT Time Received Transmit WaveformsReceiver Clock Recovery CSMA/CD Clock RecoveryDetermining Receiver Errors External ClockingRcbat Crce AddressingDetermining Line Discipline 2 CPU/DMA Control of the GSCCollisions and Backoff What the GSC was doing Response GSC Register Descriptions Successful Ending of Transmissions and ReceptionsGMOD84H Xtclk PL1 PL0 PL1 PL0 Length BitsKawasaki LSI USA, Inc Ver .9 KS152JB2 DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 ARB REQ Garen Xrclk Gfien IDLRcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc Ver .9 KS152JB2 LNI Noack Tcdt TDN Tfnf TEN DMA Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Operation DMA with the 80C152DMA Registers Alternate Cycle Mode Burst ModeDAS IDA SAS ISASerial Port Demand Mode External Demand ModeTiming Diagrams 12 OSC.PERIODS ALE Psen P1 Inst FloatPCH P2 SFR DMA Cycle Resume Program Execution DMA Transfer from Internal Memory to Internal MemoryDMA Cycle Resume Program Execution 12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCHDMA Cycle 12 OSC. Periods Resume Program Execution ALE Psen Hold/Hold Acknowledge Request ModeArbiter Mode Using the HOLD/HLDA Acknowledge ARB REQDmxrq ALE ARB If Hlda = ALE AEQ ALE REQInternal Logic of the Arbiter Internal Logic of the Requester DMA Arbitration Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Arbitration with Hold/Hold Ack Summary of DMA Control Bits DAS IDA SAS ISA DoneInterrupt Structure IE0 TI+RI ET1 EX1 ET0 EX0PT1 PX1 PT0 PX0 IPN1GSC Transmitter Error Conditions Transmit Error Flags Logic for Clearing TEN, Setting TDNGSC Receiver Error Conditions Glossary Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCON0/1 092H,093H Xtclk PL1 PL0 Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2 PT1 PX1 PT0 EX0 Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Smod ARB REQ Garen Xrclk Gfien IDL OVR Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2 SM0 SM1 SM2 REN TB8 RB8 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0Gate Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2 Port Stack PointerData Pointer LOW DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0Timer Control Data Pointer HighDPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0 DPHTimer Mode Control Gate TimerTimer 0 LSB Timer 1 LSBTimer 0 MSB Timer 1 MSBSerial Port Control SM0Serial Data Buffer SBUF.7Program Status Word RS1 RS0Accumulator ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0Kawasaki LSI USA, Inc 119 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2