Contents
Introduction
Technical Specifications
Pin Name Alternate Function
Pin Description
PIN Description
Name Description Port
XTAL2
XTAL1
RST
Epsen
ALE
Psen
Eben
SFR map for the cpu
Special function Registers
Reset Timing Reset Values of the SFRs
Pcon
Configurations
Scon
Sbuf Indeterminate Tmod
Port bit I/O Pads
Port 0 I/O Pad Port 2 I/O Pad
Ports 4,5
Fetch via
Program
Psen Epsen
Comments
Tmod Timer/Counter Mode Control Register
TIMER/COUNTERS
Mode
Tcon Timer/Counter Control Register
Timer/Counter in Mode
IE Interrupt Enable Register
Timer/Counter 0 in Mode
Interrupts
Priority Level Structure
Pgste PDMA1 Pgstv PDMA0 Pgsre Pgsrv
Egste EDMA1 Egstv EDMA0 Egsre Egsrv
Egsrv 2BH
PX0
EX0
Pgsrv
ET1 1BH
PDMA1
EDMA1
PT1
Kawasaki LSI USA, Inc Ver .9 KS152JB2
Status of the External Pins during Idle and Power Down
Power Down and Idle
ALE Psen
Smod IDL
Pcon Power Control Register
Local Serial Channel
Controller
Local Serial Port Mode
Serial Port Mode
Mode
Load Sbuf
Baud Rates
Smod
Timer 1 generated commonly used Baud rates
MHZ
JNB
SINGLE-STEP Operation
Reti
Kawasaki LSI USA Inc
Introduction
Global Serial Channel
DC JAM CRC
11/IDLE CRC None
11/IDLE
Csma Sdlc
External clock Internal clock
Control cpu Control dma Raw Receive Raw Transmit
CSMA/CD Frame Format
CSMA/CD Overview
Preamble BOF Address Info CRC EOF
Kawasaki LSI USA, Inc Ver .9 KS152JB2
23 24
Interframe Space
Jitter Tolerance
CSMA/CD Data Encoding
Manchester Encoding BIT Time
Collision Detection
Missing 0-to-1 Transition
Narrow Pulses
Unexpected 1-to-0 Transition
Tfifo
Resolution of Collisions
GSC Inactive
Response to a Detected Collision What the GSC was doing
DCR
Backoff
Algorithm
Prbs Tcdcnt Load Bkoff Slot Clock Myslot
Random Backoff
BKOFF= Myslot
Deterministic Backoff
Hardware Based Acknowledge
Kawasaki LSI USA, Inc Ver .9 KS152JB2
BOF Address Control Info CRC EOF
Sdlc Frame Format
Kawasaki LSI USA, Inc Ver .9 KS152JB2
Nrzi BIT Time
Data Encoding
BIT STUFFING/STRIPPING
Line Idle
Sending Abort Character
Acknowledgement
Ring Network
PRIMARY/SECONDARY Stations
Point-to-point Network
Multi-Drop Network
User Defined Protocols
Using a Preamble in Sdlc
HDLC/SDLC Comparison
Sdlc Hdlc
Planning for Network Changes and Expansions
Line Discipline
DMA Servicing of GSC Channels
Kawasaki LSI USA, Inc Ver .9 KS152JB2
Baud Rate
Initialization
External Driver Interface
Test Modes
Jitter Receive
Transmit Waveforms
Local Value Manchester Encoding BIT Time
Receive Sampling Rate Received
BIT Time Received
CSMA/CD Clock Recovery
Receiver Clock Recovery
Addressing
Determining Receiver Errors
External Clocking
Rcbat Crce
2 CPU/DMA Control of the GSC
Determining Line Discipline
Collisions and Backoff
What the GSC was doing Response
Successful Ending of Transmissions and Receptions
GSC Register Descriptions
PL1 PL0 Length Bits
GMOD84H Xtclk PL1 PL0
Kawasaki LSI USA, Inc Ver .9 KS152JB2
ARB REQ Garen Xrclk Gfien IDL
DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0
Rcabt Crce RDN Rfne Gren Haben
Kawasaki LSI USA, Inc Ver .9 KS152JB2
LNI Noack Tcdt TDN Tfnf TEN DMA
Kawasaki LSI USA, Inc Ver .9 KS152JB2
DMA with the 80C152
DMA Operation
DMA Registers
SAS ISA
Alternate Cycle Mode
Burst Mode
DAS IDA
External Demand Mode
Serial Port Demand Mode
DMA Transfer from Internal Memory to Internal Memory
Timing Diagrams
12 OSC.PERIODS ALE Psen P1 Inst Float
PCH P2 SFR DMA Cycle Resume Program Execution
DMA Cycle 12 OSC. Periods Resume Program Execution ALE Psen
12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCH
DMA Cycle Resume Program Execution
Arbiter Mode
Request Mode
Hold/Hold Acknowledge
ARB REQ
Using the HOLD/HLDA Acknowledge
Internal Logic of the Arbiter
ALE ARB If Hlda = ALE AEQ ALE REQ
Dmxrq
Internal Logic of the Requester
DMA Arbitration
Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2
Kawasaki LSI USA, Inc Ver .9 KS152JB2
Kawasaki LSI USA, Inc Ver .9 KS152JB2
DMA Arbitration with Hold/Hold Ack
DAS IDA SAS ISA Done
Summary of DMA Control Bits
Interrupt Structure
IE0
ET1 EX1 ET0 EX0
TI+RI
IPN1
PT1 PX1 PT0 PX0
Transmit Error Flags Logic for Clearing TEN, Setting TDN
GSC Transmitter Error Conditions
GSC Receiver Error Conditions
Glossary
Kawasaki LSI USA, Inc Ver .9 KS152JB2
DCON0/1 092H,093H
Xtclk PL1 PL0
Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2
Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2
PT1 PX1 PT0 EX0
Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0
Smod ARB REQ Garen Xrclk Gfien IDL
OVR Rcabt Crce RDN Rfne Gren Haben
Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
SM0 SM1 SM2 REN TB8 RB8
Gate
Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2
DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0
Port
Stack Pointer
Data Pointer LOW
DPH
Timer Control
Data Pointer High
DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0
Timer 1 LSB
Timer Mode Control
Gate Timer
Timer 0 LSB
Timer 1 MSB
Timer 0 MSB
SBUF.7
Serial Port Control
SM0
Serial Data Buffer
RS1 RS0
Program Status Word
ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0
Accumulator
Kawasaki LSI USA, Inc 119 Ver .9 KS152JB2
Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2