Kawasaki 80C152, KS152JB, 80C51 technical specifications Kawasaki LSI USA Inc

Page 31

Kawasaki LSI USA Inc.

Table 8: Instruction Table

lsn

0

1

2

3

4

5

6-7

8-F

msn

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

nop

ajmp

ljmp

rr a

inc a

inc d

inc @

inc rn

 

 

 

 

 

 

 

 

 

1

jbc

acall

lcall

rrc a

dec a

dec d

dec @

dec rn

 

 

 

 

 

 

 

 

 

2

jb

ajmp

ret

rl a

add a, #

add a, d

add a, @

add a, rn

 

 

 

 

 

 

 

 

 

3

jnb

acall

reti

rlc a

addc a, #

addc a, d

addc a, @

addc a, rn

 

 

 

 

 

 

 

 

 

4

jc

ajmp

orl d, a

orl d, #

orl a, #

orl a, d

orl a, @

orl a, rn

 

 

 

 

 

 

 

 

 

5

jnc

acall

anl d, a

anl d, #

anl a, #

anl a, d

anl a, @

anl a, rn

 

 

 

 

 

 

 

 

 

6

jz

ajmp

xrl d, a

xrl d, #

xrl a, #

xrl a, d

xrl a, @

xrl a, rn

 

 

 

 

 

 

 

 

 

7

jnz

acall

orl c, bit

jmp @a+dptr

mov a, #

mov d, #

mov @, #

mov rn, #

 

 

 

 

 

 

 

 

 

8

sjmp

ajmp

anl c, bit

movc a, @a+pc

div ab

mov d, d

mov d, @

mov d, rn

 

 

 

 

 

 

 

 

 

9

mov dptr, #

acall

mov bit, c

movc a,

subb a, #

subb a, d

subb a, @

subb a, rn

 

 

 

 

@a+dptr

 

 

 

 

 

 

 

 

 

 

 

 

 

A

orl c, /bit

ajmp

mov c, bit

inc dptr

mul ab

dec dptr

mov @, d

mov rn, d

 

 

 

 

 

 

 

 

 

B

anl c, /bit

acall

cp bit

cpl c

cjne a, #, rel

cjne a, d, rel

cjne @, #, rel

cjne rn, #, rel

 

 

 

 

 

 

 

 

 

C

push

ajmp

clr bit

clr c

swap a

xch a, d

xch a, @

xch a, rn

 

 

 

 

 

 

 

 

 

D

pop

acall

setb bit

setb c

da a

djnz d, rel

xchd a, @

djnz rn, rel

 

 

 

 

 

 

 

 

 

E

movx a, @dptr

ajmp

movx a, @r0

movx a, @r1

clr a

mov a, d

mov a, @

mov a, rn

 

 

 

 

 

 

 

 

 

F

movx @dptr, a

acall

movx @r0, a

movx @r1, a

cpl a

mov d, a

mov @, a

mov rn , a

 

 

 

 

 

 

 

 

 

KS152JB Universal Communications Controller Technical Specifications

Image 31
Contents Introduction Technical Specifications Pin Name Alternate Function Pin DescriptionPIN Description Name Description PortXTAL2 XTAL1RST Epsen ALEPsen EbenSFR map for the cpu Special function RegistersReset Timing Reset Values of the SFRs Pcon ConfigurationsScon Sbuf Indeterminate TmodPort bit I/O Pads Port 0 I/O Pad Port 2 I/O PadPorts 4,5 Fetch via ProgramPsen Epsen CommentsTmod Timer/Counter Mode Control Register TIMER/COUNTERSMode Tcon Timer/Counter Control RegisterTimer/Counter in Mode IE Interrupt Enable Register Timer/Counter 0 in ModeInterrupts Priority Level Structure Pgste PDMA1 Pgstv PDMA0 Pgsre Pgsrv Egste EDMA1 Egstv EDMA0 Egsre EgsrvEgsrv 2BH PX0EX0 PgsrvET1 1BH PDMA1EDMA1 PT1Kawasaki LSI USA, Inc Ver .9 KS152JB2 Status of the External Pins during Idle and Power Down Power Down and IdleALE Psen Smod IDL Pcon Power Control RegisterLocal Serial Channel Controller Local Serial Port ModeSerial Port Mode Mode Load Sbuf Baud Rates Smod Timer 1 generated commonly used Baud ratesMHZ JNB SINGLE-STEP OperationReti Kawasaki LSI USA Inc Introduction Global Serial ChannelDC JAM CRC 11/IDLE CRC None11/IDLE Csma SdlcExternal clock Internal clock Control cpu Control dma Raw Receive Raw Transmit CSMA/CD Frame Format CSMA/CD OverviewPreamble BOF Address Info CRC EOF Kawasaki LSI USA, Inc Ver .9 KS152JB2 23 24 Interframe Space Jitter Tolerance CSMA/CD Data EncodingManchester Encoding BIT Time Collision DetectionMissing 0-to-1 Transition Narrow PulsesUnexpected 1-to-0 Transition Tfifo Resolution of CollisionsGSC Inactive Response to a Detected Collision What the GSC was doingDCR BackoffAlgorithm Prbs Tcdcnt Load Bkoff Slot Clock Myslot Random BackoffBKOFF= Myslot Deterministic Backoff Hardware Based Acknowledge Kawasaki LSI USA, Inc Ver .9 KS152JB2 BOF Address Control Info CRC EOF Sdlc Frame FormatKawasaki LSI USA, Inc Ver .9 KS152JB2 Nrzi BIT Time Data EncodingBIT STUFFING/STRIPPING Line Idle Sending Abort CharacterAcknowledgement Ring Network PRIMARY/SECONDARY StationsPoint-to-point Network Multi-Drop NetworkUser Defined Protocols Using a Preamble in SdlcHDLC/SDLC Comparison Sdlc HdlcPlanning for Network Changes and Expansions Line DisciplineDMA Servicing of GSC Channels Kawasaki LSI USA, Inc Ver .9 KS152JB2 Baud Rate Initialization External Driver Interface Test ModesJitter Receive Transmit Waveforms Local Value Manchester Encoding BIT TimeReceive Sampling Rate Received BIT Time ReceivedCSMA/CD Clock Recovery Receiver Clock RecoveryAddressing Determining Receiver ErrorsExternal Clocking Rcbat Crce2 CPU/DMA Control of the GSC Determining Line DisciplineCollisions and Backoff What the GSC was doing Response Successful Ending of Transmissions and Receptions GSC Register DescriptionsPL1 PL0 Length Bits GMOD84H Xtclk PL1 PL0Kawasaki LSI USA, Inc Ver .9 KS152JB2 ARB REQ Garen Xrclk Gfien IDL DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc Ver .9 KS152JB2 LNI Noack Tcdt TDN Tfnf TEN DMA Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA with the 80C152 DMA OperationDMA Registers SAS ISA Alternate Cycle ModeBurst Mode DAS IDAExternal Demand Mode Serial Port Demand ModeDMA Transfer from Internal Memory to Internal Memory Timing Diagrams12 OSC.PERIODS ALE Psen P1 Inst Float PCH P2 SFR DMA Cycle Resume Program ExecutionDMA Cycle 12 OSC. Periods Resume Program Execution ALE Psen 12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCHDMA Cycle Resume Program Execution Arbiter Mode Request ModeHold/Hold Acknowledge ARB REQ Using the HOLD/HLDA AcknowledgeInternal Logic of the Arbiter ALE ARB If Hlda = ALE AEQ ALE REQDmxrq Internal Logic of the Requester DMA Arbitration Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Arbitration with Hold/Hold Ack DAS IDA SAS ISA Done Summary of DMA Control BitsInterrupt Structure IE0 ET1 EX1 ET0 EX0 TI+RIIPN1 PT1 PX1 PT0 PX0Transmit Error Flags Logic for Clearing TEN, Setting TDN GSC Transmitter Error ConditionsGSC Receiver Error Conditions Glossary Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCON0/1 092H,093H Xtclk PL1 PL0 Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2 PT1 PX1 PT0 EX0 Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Smod ARB REQ Garen Xrclk Gfien IDL OVR Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 SM0 SM1 SM2 REN TB8 RB8Gate Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2 DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0 PortStack Pointer Data Pointer LOWDPH Timer ControlData Pointer High DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0Timer 1 LSB Timer Mode ControlGate Timer Timer 0 LSBTimer 1 MSB Timer 0 MSBSBUF.7 Serial Port ControlSM0 Serial Data BufferRS1 RS0 Program Status WordACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 AccumulatorKawasaki LSI USA, Inc 119 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2