Kawasaki 80C51, KS152JB, 80C152 technical specifications Program, Psen Epsen, Comments, Fetch via

Page 11

KS152JB Universal Communications Controller Technical Specifications

Table 4:

 

 

 

 

 

 

 

 

 

 

 

 

 

EBEN

 

EA

Program

 

PSEN

 

EPSEN

Comments

 

 

 

 

Fetch via

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

 

P0, P2

Active

Inactive

Addresses 0

- 0FFFFH

 

 

 

 

 

 

 

 

 

 

 

 

0

1

 

N/A

 

N/A

 

N/A

Invalid Combination

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

 

P5, P6

Inactive

 

 

 

Addresses 0

- 0FFFFH

 

 

 

 

 

 

 

 

 

 

 

 

 

1

1

 

P5, P6

Inactive

 

Active

Addresses 0

- 1FFFH

 

 

 

 

P0, P2

 

Active

Inactive

Addresses 0

- 2000H

 

 

 

 

 

 

 

 

 

 

 

 

 

2.6 ACCESSING EXTERNAL MEMORY

External Memory is accessed if either of the following two conditions is met

1)The signal EA is low

2)Whenever the program counter (PC) contains an address greater than 0FFFh.

Accesses to external memory are of two type: External Program Memory accesses and External Data Memory accesses. External Program Memory is accessed using the PSEN signal as the read strobe. External Data Memory is accessed using the RD or WR pins to strobe the memory.

Fetches from the external Program Memory always use a 16 bit address, while External Data Memory accesses can have addresses of 8 bit or 16 bit. Whenever a 16 bit address is used, Port 2 is used to emit the higher byte of the address. The point to note is that during external accesses, port 2 uses strong pullups while emitting 1s. During the time Port 2 does not emit the higher address byte, it continuously outputs the Port 2 SFR contents, which are not modified by the hard- ware (unless of course the user writes to the Port 2 SFR). If an 8 bit address is being used, then the Port 2 SFR contents will be outputed on the port pins throughout the external memory cycle.

The lower byte of the address is always multiplexed with the data byte on Port 0. The ADDR/ DATA bus can drive both the active pullup and pulldown FETs. Thus for external memory accesses, the port 0 pins are not open-drain outputs and do not need any external pullups. The fall- ing edge of the ALE signal can be used to store the address on Ports 0 and 2 in an external address latch. During a write cycle, the data to be written to the external Data Memory is present on Port 0 pins and remains there until after WR is deactivated. In case of a read access, the data on Port 0 pins is read just before the deactivation of the RD signal.

During accesses to external memory, the CPU presets the Port 0 SFR to FFh in order to float the Port 0 pins. Therefore any data that was present in the SFR latch will be lost. If the user, writes any data other than FFh to Port 0 during an external memory cycle, then the incoming code byte will be corrupted. Therefore, DO NOT WRITE TO Port 0 if external memory is used.

Kawasaki LSI USA, Inc.

Page 11 of 120

Ver. 0.9 KS152JB2

Page 10 Page 12
Image 11
Page 10 Page 12
Contents Introduction Technical Specifications Pin Name Alternate Function Pin DescriptionPIN Description Name Description PortRST XTAL1XTAL2 Epsen ALEPsen EbenSFR map for the cpu Special function RegistersReset Timing Reset Values of the SFRs Pcon ConfigurationsScon Sbuf Indeterminate TmodPort bit I/O Pads Port 0 I/O Pad Port 2 I/O PadPorts 4,5 Fetch via ProgramPsen Epsen CommentsTmod Timer/Counter Mode Control Register TIMER/COUNTERSMode Tcon Timer/Counter Control RegisterTimer/Counter in Mode Interrupts Timer/Counter 0 in ModeIE Interrupt Enable Register Priority Level Structure Pgste PDMA1 Pgstv PDMA0 Pgsre Pgsrv Egste EDMA1 Egstv EDMA0 Egsre EgsrvEgsrv 2BH PX0EX0 PgsrvET1 1BH PDMA1EDMA1 PT1Kawasaki LSI USA, Inc Ver .9 KS152JB2 ALE Psen Power Down and IdleStatus of the External Pins during Idle and Power Down Smod IDL Pcon Power Control RegisterLocal Serial Channel Controller Local Serial Port ModeSerial Port Mode Mode Load Sbuf Baud Rates MHZ Timer 1 generated commonly used Baud ratesSmod Reti SINGLE-STEP OperationJNB Kawasaki LSI USA Inc Introduction Global Serial ChannelDC JAM CRC 11/IDLE CRC None11/IDLE Csma SdlcExternal clock Internal clock Control cpu Control dma Raw Receive Raw Transmit Preamble BOF Address Info CRC EOF CSMA/CD OverviewCSMA/CD Frame Format Kawasaki LSI USA, Inc Ver .9 KS152JB2 23 24 Interframe Space Jitter Tolerance CSMA/CD Data EncodingManchester Encoding BIT Time Collision DetectionUnexpected 1-to-0 Transition Narrow PulsesMissing 0-to-1 Transition Tfifo Resolution of CollisionsGSC Inactive Response to a Detected Collision What the GSC was doingAlgorithm BackoffDCR BKOFF= Myslot Random BackoffPrbs Tcdcnt Load Bkoff Slot Clock Myslot Deterministic Backoff Hardware Based Acknowledge Kawasaki LSI USA, Inc Ver .9 KS152JB2 BOF Address Control Info CRC EOF Sdlc Frame FormatKawasaki LSI USA, Inc Ver .9 KS152JB2 BIT STUFFING/STRIPPING Data EncodingNrzi BIT Time Acknowledgement Sending Abort CharacterLine Idle Ring Network PRIMARY/SECONDARY StationsPoint-to-point Network Multi-Drop NetworkUser Defined Protocols Using a Preamble in SdlcHDLC/SDLC Comparison Sdlc HdlcPlanning for Network Changes and Expansions Line DisciplineDMA Servicing of GSC Channels Kawasaki LSI USA, Inc Ver .9 KS152JB2 Baud Rate Initialization External Driver Interface Test ModesJitter Receive Transmit Waveforms Local Value Manchester Encoding BIT TimeReceive Sampling Rate Received BIT Time ReceivedCSMA/CD Clock Recovery Receiver Clock RecoveryAddressing Determining Receiver ErrorsExternal Clocking Rcbat Crce2 CPU/DMA Control of the GSC Determining Line DisciplineCollisions and Backoff What the GSC was doing Response Successful Ending of Transmissions and Receptions GSC Register DescriptionsPL1 PL0 Length Bits GMOD84H Xtclk PL1 PL0Kawasaki LSI USA, Inc Ver .9 KS152JB2 ARB REQ Garen Xrclk Gfien IDL DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc Ver .9 KS152JB2 LNI Noack Tcdt TDN Tfnf TEN DMA Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA with the 80C152 DMA OperationDMA Registers SAS ISA Alternate Cycle ModeBurst Mode DAS IDAExternal Demand Mode Serial Port Demand ModeDMA Transfer from Internal Memory to Internal Memory Timing Diagrams12 OSC.PERIODS ALE Psen P1 Inst Float PCH P2 SFR DMA Cycle Resume Program ExecutionDMA Cycle Resume Program Execution 12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCHDMA Cycle 12 OSC. Periods Resume Program Execution ALE Psen Hold/Hold Acknowledge Request ModeArbiter Mode ARB REQ Using the HOLD/HLDA AcknowledgeDmxrq ALE ARB If Hlda = ALE AEQ ALE REQInternal Logic of the Arbiter Internal Logic of the Requester DMA Arbitration Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Arbitration with Hold/Hold Ack DAS IDA SAS ISA Done Summary of DMA Control BitsInterrupt Structure IE0 ET1 EX1 ET0 EX0 TI+RIIPN1 PT1 PX1 PT0 PX0Transmit Error Flags Logic for Clearing TEN, Setting TDN GSC Transmitter Error ConditionsGSC Receiver Error Conditions Glossary Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCON0/1 092H,093H Xtclk PL1 PL0 Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2 PT1 PX1 PT0 EX0 Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Smod ARB REQ Garen Xrclk Gfien IDL OVR Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 SM0 SM1 SM2 REN TB8 RB8Gate Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2 DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0 PortStack Pointer Data Pointer LOWDPH Timer ControlData Pointer High DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0Timer 1 LSB Timer Mode ControlGate Timer Timer 0 LSBTimer 1 MSB Timer 0 MSBSBUF.7 Serial Port ControlSM0 Serial Data BufferRS1 RS0 Program Status WordACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 AccumulatorKawasaki LSI USA, Inc 119 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2
Top Page Image Contents