Kawasaki 80C152, KS152JB, 80C51 technical specifications Interframe Space

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KS152JB Universal Communications Controller Technical Specifications

link remains high for 2 or more bit times.

3.2.3 INTERFRAME SPACE

The interframe space is the amount of time that transmission is delayed after the link is sensed as being idle and is used to separate transmitted frames. In alternate back off mode, the interframe space may also be included in the determination of when retransmissions may actually begin. The C152 allows programmable interframe spaces of even numbers of times from 2 to 256. The hard- ware enforces the interframe space in SDLC mode as well as in CSMA/CD mode.

The period of the interframe space is determined by the contents of IFS. IFS is an SFR that is pro- grammable from 0 to 254. The interframe space is measured in bit times. The value in IFS multi- plied by the bit time equals the interframe space unless IFS equals 0. If IFS does equal 0, then the interframe space will equal 256 bit times. One of the considerations when loading the IFS is that only even numbers (LSB must be 0) can be used because only the 7 most significant bits are loaded into IFS. The LSB is controlled by the GSC and determines which half of the IFS is cur- rently being used. In some modes, the interframe space timer is re-triggered if activity is detected during the first half of the period. The GSC determines which half of the interframe space is cur- rently being used by examining the LSB. A one indicates the first half and zero indicates the sec- ond half of the IFS.

After reset IFS is 0, which delays the first transmission for both SDLC and CSMA/CD by 256 bit times (after reset, a bit time equals 8 oscillator clock periods).

In most applications, the period of the interframe space will be equal to or greater than the amount of time needed to turn -around the received frame. The turn-around period is the amount of time that is needed by user software to complete the handling of a received frame and be prepared to receive the next frame. An interframe space smaller than the required turn-around period could be used, but would allow some frames to be missed.

When a GSC transmitter has a new message to send, it will first sense the link. If activity is detected, transmission will be deferred to allow the frame in progress to complete. When link activity ceases, the station continues deferring for one interframe space period.

As mentioned earlier, the interframe space is used during the collision resolution period as well as during normal transmission. The backoff method selected affects how the deference period is han- dled during normal transmission. If normal backoff mode is selected, the interframe space timer is reset if activity occurs during approximately the first half of the interframe space. If alternate backoff or deterministic backoff is selected, the timer is not reset. In all cases when the interframe space timer expires, transmission may begin, regardless if there is activity on the link or not. Although the C152 resets the interframe space timer if activity is detected during the first one-half of the interframe space, this is not necessarily true of all CSMA/CD systems. (IEEE 802.3 recom- mends that the interframe space be reset if activity is detected during the first two-thirds or less of the interframe space.)

Kawasaki LSI USA, Inc.

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Ver. 0.9 KS152JB2

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Contents Introduction Technical Specifications Pin Description PIN DescriptionName Description Port Pin Name Alternate FunctionXTAL2 XTAL1RST ALE PsenEben EpsenSpecial function Registers SFR map for the cpuReset Timing Reset Values of the SFRs Configurations SconSbuf Indeterminate Tmod PconPort 0 I/O Pad Port 2 I/O Pad Port bit I/O PadsPorts 4,5 Program Psen EpsenComments Fetch viaTIMER/COUNTERS Tmod Timer/Counter Mode Control RegisterTcon Timer/Counter Control Register ModeTimer/Counter in Mode IE Interrupt Enable Register Timer/Counter 0 in ModeInterrupts Priority Level Structure Egste EDMA1 Egstv EDMA0 Egsre Egsrv Pgste PDMA1 Pgstv PDMA0 Pgsre PgsrvPX0 EX0Pgsrv Egsrv 2BHPDMA1 EDMA1PT1 ET1 1BHKawasaki LSI USA, Inc Ver .9 KS152JB2 Status of the External Pins during Idle and Power Down Power Down and IdleALE Psen Pcon Power Control Register Smod IDLLocal Serial Channel Local Serial Port Mode ControllerSerial Port Mode Mode Load Sbuf Baud Rates Smod Timer 1 generated commonly used Baud ratesMHZ JNB SINGLE-STEP OperationReti Kawasaki LSI USA Inc Global Serial Channel Introduction11/IDLE CRC None DC JAM CRCCsma Sdlc 11/IDLEExternal clock Internal clock Control cpu Control dma Raw Receive Raw Transmit CSMA/CD Frame Format CSMA/CD Overview Preamble BOF Address Info CRC EOF Kawasaki LSI USA, Inc Ver .9 KS152JB2 23 24 Interframe Space CSMA/CD Data Encoding Manchester Encoding BIT TimeCollision Detection Jitter ToleranceMissing 0-to-1 Transition Narrow PulsesUnexpected 1-to-0 Transition Resolution of Collisions GSC InactiveResponse to a Detected Collision What the GSC was doing TfifoDCR BackoffAlgorithm Prbs Tcdcnt Load Bkoff Slot Clock Myslot Random BackoffBKOFF= Myslot Deterministic Backoff Hardware Based Acknowledge Kawasaki LSI USA, Inc Ver .9 KS152JB2 Sdlc Frame Format BOF Address Control Info CRC EOFKawasaki LSI USA, Inc Ver .9 KS152JB2 Nrzi BIT Time Data EncodingBIT STUFFING/STRIPPING Line Idle Sending Abort CharacterAcknowledgement PRIMARY/SECONDARY Stations Point-to-point NetworkMulti-Drop Network Ring NetworkUsing a Preamble in Sdlc HDLC/SDLC ComparisonSdlc Hdlc User Defined ProtocolsLine Discipline Planning for Network Changes and ExpansionsDMA Servicing of GSC Channels Kawasaki LSI USA, Inc Ver .9 KS152JB2 Baud Rate Initialization Test Modes External Driver InterfaceJitter Receive Local Value Manchester Encoding BIT Time Receive Sampling Rate ReceivedBIT Time Received Transmit WaveformsReceiver Clock Recovery CSMA/CD Clock RecoveryDetermining Receiver Errors External ClockingRcbat Crce AddressingDetermining Line Discipline 2 CPU/DMA Control of the GSCCollisions and Backoff What the GSC was doing Response GSC Register Descriptions Successful Ending of Transmissions and ReceptionsGMOD84H Xtclk PL1 PL0 PL1 PL0 Length BitsKawasaki LSI USA, Inc Ver .9 KS152JB2 DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 ARB REQ Garen Xrclk Gfien IDLRcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc Ver .9 KS152JB2 LNI Noack Tcdt TDN Tfnf TEN DMA Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Operation DMA with the 80C152DMA Registers Alternate Cycle Mode Burst ModeDAS IDA SAS ISASerial Port Demand Mode External Demand ModeTiming Diagrams 12 OSC.PERIODS ALE Psen P1 Inst FloatPCH P2 SFR DMA Cycle Resume Program Execution DMA Transfer from Internal Memory to Internal MemoryDMA Cycle 12 OSC. Periods Resume Program Execution ALE Psen 12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCHDMA Cycle Resume Program Execution Arbiter Mode Request ModeHold/Hold Acknowledge Using the HOLD/HLDA Acknowledge ARB REQInternal Logic of the Arbiter ALE ARB If Hlda = ALE AEQ ALE REQDmxrq Internal Logic of the Requester DMA Arbitration Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Arbitration with Hold/Hold Ack Summary of DMA Control Bits DAS IDA SAS ISA DoneInterrupt Structure IE0 TI+RI ET1 EX1 ET0 EX0PT1 PX1 PT0 PX0 IPN1GSC Transmitter Error Conditions Transmit Error Flags Logic for Clearing TEN, Setting TDNGSC Receiver Error Conditions Glossary Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCON0/1 092H,093H Xtclk PL1 PL0 Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2 PT1 PX1 PT0 EX0 Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Smod ARB REQ Garen Xrclk Gfien IDL OVR Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2 SM0 SM1 SM2 REN TB8 RB8 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0Gate Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2 Port Stack PointerData Pointer LOW DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0Timer Control Data Pointer HighDPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0 DPHTimer Mode Control Gate TimerTimer 0 LSB Timer 1 LSBTimer 0 MSB Timer 1 MSBSerial Port Control SM0Serial Data Buffer SBUF.7Program Status Word RS1 RS0Accumulator ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0Kawasaki LSI USA, Inc 119 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2
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