Kawasaki KS152JB, 80C152, 80C51 technical specifications Collisions and Backoff

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KS152JB Universal Communications Controller Technical Specifications

and then writing to TFIFO. TEN must be set before loading the transmit FIFO, as setting TEN clears the transmit FIFO. TCDCNT should also be checked by user software and cleared if a col- lision occurred on a prior transmission.

To enable the receiver, GREN (RSTAT.1) is set. After GREN is set, the GSC begins to look for a valid BOF. After detecting a valid BOF the GSC attempts to match the received address byte(s) against the address match registers. When a match occurs the frame is loaded into the GSC. Due to the CRC strip hardware, there is a 40 or 24 bit time delay following the BOF until the first data byte is loaded into RFIFO if the 32 or 16 bit CRC is chosen. If the end of frame is detected before data is loaded into the receive FIFO, the receiver ignores that frame.

If the receiver detects a collision during reception in CSMA/CD mode and if any bytes have been loaded into the receive FIFO, the RCABT flag is set. The GSC hardware then halts reception and resets GREN. The user software needs to filter any collision fragment data which may have been received. If the collision occurred prior to the data being loaded into RFIFO the CPU is not noti- fied and the receiver is left enabled. At the end of a reception the RDN bit is set and GREN is cleared. In HABEN mode this causes an acknowledgment to be transmitted if the frame did not have a broadcast or multi-cast address. The user software can enable the interrupt for RDN to determine when a frame is completed.

In DMA mode the interrupts are generated by the internal “transmit/receive done” (TDN,RDN) conditions. When the CPU responds to TDN or RDN, checks are performed to see if the transmit underrun error has occurred. The underrun condition is only checked when using the DMA chan- nels.

Upon power up the CPU mode is initialized. General DMA control is covered in Section 4.0 DMA control of the GSC is covered in Section 3.5.4. If DMA is to be used for serving the GSC, it must be configured into the serial channel demand mode and the DMA bit in TSTAT has to be set.

3.6.3 COLLISIONS AND BACKOFF

The actions that are taken by the GSC if a collision occurs while transmitting depend on where the collision occurs. If a collision occurs in CSMA/CD mode following the preamble and BOF flag, the TCDT flag is set and the transmit hardware completes a jam. When this type of collision occurs, there will be no automatic retry at transmission. After the jam, control is returned to the CPU and user software must then initiate whatever actions are necessary for a proper recovery. The possibility that data might have been loaded into or from the GSC deserves special consider- ation. If these fragments of a message have been passed on to other devices, user software may have to perform some extensive error handling or notification. Before starting a new message, the transmit and receive FIFOs will need to be cleared. If DMA servicing is being used the pointers must also be reinitialized. It should be noted that a collision should never occur after the BOF flag in a well designed system, since the system slot time will likely be less than the preamble length. The occurrence of such a situation is normally due to a station on the link that is not adhering to proper CSMA/CD protocol or is not using the same timing s as the rest of the network.

A collision occurring during the preamble or BOF flag is the normal type of collision that is

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Ver. 0.9 KS152JB2

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Contents Introduction Technical Specifications Name Description Port Pin DescriptionPIN Description Pin Name Alternate FunctionXTAL1 XTAL2RST Eben ALEPsen EpsenSpecial function Registers SFR map for the cpuReset Timing Reset Values of the SFRs Sbuf Indeterminate Tmod ConfigurationsScon PconPort 0 I/O Pad Port 2 I/O Pad Port bit I/O PadsPorts 4,5 Comments ProgramPsen Epsen Fetch viaTIMER/COUNTERS Tmod Timer/Counter Mode Control RegisterTcon Timer/Counter Control Register ModeTimer/Counter in Mode Timer/Counter 0 in Mode IE Interrupt Enable RegisterInterrupts Priority Level Structure Egste EDMA1 Egstv EDMA0 Egsre Egsrv Pgste PDMA1 Pgstv PDMA0 Pgsre PgsrvPgsrv PX0EX0 Egsrv 2BHPT1 PDMA1EDMA1 ET1 1BHKawasaki LSI USA, Inc Ver .9 KS152JB2 Power Down and Idle Status of the External Pins during Idle and Power DownALE Psen Pcon Power Control Register Smod IDLLocal Serial Channel Local Serial Port Mode ControllerSerial Port Mode Mode Load Sbuf Baud Rates Timer 1 generated commonly used Baud rates SmodMHZ SINGLE-STEP Operation JNBReti Kawasaki LSI USA Inc Global Serial Channel Introduction11/IDLE CRC None DC JAM CRCCsma Sdlc 11/IDLEExternal clock Internal clock Control cpu Control dma Raw Receive Raw Transmit CSMA/CD Overview CSMA/CD Frame FormatPreamble BOF Address Info CRC EOF Kawasaki LSI USA, Inc Ver .9 KS152JB2 23 24 Interframe Space Collision Detection CSMA/CD Data EncodingManchester Encoding BIT Time Jitter ToleranceNarrow Pulses Missing 0-to-1 TransitionUnexpected 1-to-0 Transition Response to a Detected Collision What the GSC was doing Resolution of CollisionsGSC Inactive TfifoBackoff DCRAlgorithm Random Backoff Prbs Tcdcnt Load Bkoff Slot Clock MyslotBKOFF= Myslot Deterministic Backoff Hardware Based Acknowledge Kawasaki LSI USA, Inc Ver .9 KS152JB2 Sdlc Frame Format BOF Address Control Info CRC EOFKawasaki LSI USA, Inc Ver .9 KS152JB2 Data Encoding Nrzi BIT TimeBIT STUFFING/STRIPPING Sending Abort Character Line IdleAcknowledgement Multi-Drop Network PRIMARY/SECONDARY StationsPoint-to-point Network Ring NetworkSdlc Hdlc Using a Preamble in SdlcHDLC/SDLC Comparison User Defined ProtocolsLine Discipline Planning for Network Changes and ExpansionsDMA Servicing of GSC Channels Kawasaki LSI USA, Inc Ver .9 KS152JB2 Baud Rate Initialization Test Modes External Driver InterfaceJitter Receive BIT Time Received Local Value Manchester Encoding BIT TimeReceive Sampling Rate Received Transmit WaveformsReceiver Clock Recovery CSMA/CD Clock RecoveryRcbat Crce Determining Receiver ErrorsExternal Clocking AddressingDetermining Line Discipline 2 CPU/DMA Control of the GSCCollisions and Backoff What the GSC was doing Response GSC Register Descriptions Successful Ending of Transmissions and ReceptionsGMOD84H Xtclk PL1 PL0 PL1 PL0 Length BitsKawasaki LSI USA, Inc Ver .9 KS152JB2 DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 ARB REQ Garen Xrclk Gfien IDLRcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc Ver .9 KS152JB2 LNI Noack Tcdt TDN Tfnf TEN DMA Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Operation DMA with the 80C152DMA Registers DAS IDA Alternate Cycle ModeBurst Mode SAS ISASerial Port Demand Mode External Demand ModePCH P2 SFR DMA Cycle Resume Program Execution Timing Diagrams12 OSC.PERIODS ALE Psen P1 Inst Float DMA Transfer from Internal Memory to Internal Memory12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCH DMA Cycle 12 OSC. Periods Resume Program Execution ALE PsenDMA Cycle Resume Program Execution Request Mode Arbiter ModeHold/Hold Acknowledge Using the HOLD/HLDA Acknowledge ARB REQALE ARB If Hlda = ALE AEQ ALE REQ Internal Logic of the ArbiterDmxrq Internal Logic of the Requester DMA Arbitration Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Arbitration with Hold/Hold Ack Summary of DMA Control Bits DAS IDA SAS ISA DoneInterrupt Structure IE0 TI+RI ET1 EX1 ET0 EX0PT1 PX1 PT0 PX0 IPN1GSC Transmitter Error Conditions Transmit Error Flags Logic for Clearing TEN, Setting TDNGSC Receiver Error Conditions Glossary Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCON0/1 092H,093H Xtclk PL1 PL0 Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2 PT1 PX1 PT0 EX0 Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Smod ARB REQ Garen Xrclk Gfien IDL OVR Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2 SM0 SM1 SM2 REN TB8 RB8 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0Gate Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2 Data Pointer LOW PortStack Pointer DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0 Timer ControlData Pointer High DPHTimer 0 LSB Timer Mode ControlGate Timer Timer 1 LSBTimer 0 MSB Timer 1 MSBSerial Data Buffer Serial Port ControlSM0 SBUF.7Program Status Word RS1 RS0Accumulator ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0Kawasaki LSI USA, Inc 119 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2