Kawasaki 80C152, KS152JB, 80C51 technical specifications Pcon Power Control Register, Smod IDL

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KS152JB Universal Communications Controller Technical Specifications

 

7

6

 

5

4

3

2

 

1

0

 

 

SMOD

--

 

--

--

--

--

 

PD

IDL

 

 

 

 

 

 

 

 

 

 

 

SMOD

Double Baud Rate bit. When cleared, the baud rate is halved, by dividing the

 

serial clock by 2.

 

 

 

 

 

 

 

 

--

Described later.

 

 

 

 

 

 

 

 

PD

Power Down bit. Setting this bit activates this mode.

 

 

 

IDL

Idle Mode bit. Setting this bit activates this mode.

 

 

 

PCON: Power Control Register.

There are two ways to terminate the Idle mode. One way is to reset the processor and the other is by activation of any enabled interrupt. On receiving an interrupt, the processor will vector to the interrupt service routine and will start execution from here. After completion of the service rou- tine, following the execution of RETI, the execution will continue from the instruction following the one which put the processor into the Idle mode.

The signal at the RST pin is used to clear the IDL bit. The RST pin has to be held low for at least 24 clock periods to generate an internal reset. The clearing of IDL bit is done synchronously, so that the CPU will restart from the same state phase condition that it went into Idle. This ensures smooth transition from Idle mode to normal operation. Now the reset logic takes 19 clock periods to activate the internal reset from the time where RST was sampled low. For this time the proces- sor will continue operations carrying on from the next instruction which put the processor in the Idle mode. On-chip hardware prevents any writes to RAM during this period. but accesses to ports is not inhibited. To prevent unexpected outputs at the port pins, the instruction after the one which causes the Idle mode should not be an assess to the ports or External RAM.

The GSC continues to operate in Idle as long as the interrupts are enabled. The interrupts need to be enabled, so that the CPU can service the FIFO’s. In order to properly terminate a reception or transmission the C152 must not be in idle when the EOF is transmitted or received. After servic- ing the GSC, user software will need to again invoke the Idle command as the CPU does not auto- matically re-enter the Idle mode after servicing the interrupts.

The GSC does not operate while in Power Down so the steps required prior to entering Power Down become more complicated. The sequence when entering Power Down and the status of the I/O is of major importance in preventing damage to the C152 or other components in the system. since the only way to exit Power Down is with a Reset, several problems that merit careful consid- eration are cases where the Power Down occurs during the middle of a transmission, and the pos- sibility that other stations are not or cannot enter this same mode. The state of the GSC I/O pins becomes critical and the GSC status will need to be saved before power down is entered. There will also need to be some method of identifying to the CPU that the following Reset is probably not a cold start and that other stations on the link may have already been initialized.

Kawasaki LSI USA, Inc.

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Ver. 0.9 KS152JB2

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Contents Introduction Technical Specifications Name Description Port Pin DescriptionPIN Description Pin Name Alternate FunctionXTAL2 XTAL1RST Eben ALEPsen EpsenSpecial function Registers SFR map for the cpuReset Timing Reset Values of the SFRs Sbuf Indeterminate Tmod ConfigurationsScon PconPort 0 I/O Pad Port 2 I/O Pad Port bit I/O PadsPorts 4,5 Comments ProgramPsen Epsen Fetch viaTIMER/COUNTERS Tmod Timer/Counter Mode Control RegisterTcon Timer/Counter Control Register ModeTimer/Counter in Mode IE Interrupt Enable Register Timer/Counter 0 in ModeInterrupts Priority Level Structure Egste EDMA1 Egstv EDMA0 Egsre Egsrv Pgste PDMA1 Pgstv PDMA0 Pgsre PgsrvPgsrv PX0EX0 Egsrv 2BH PT1 PDMA1 EDMA1 ET1 1BHKawasaki LSI USA, Inc Ver .9 KS152JB2 Status of the External Pins during Idle and Power Down Power Down and IdleALE Psen Pcon Power Control Register Smod IDLLocal Serial Channel Local Serial Port Mode ControllerSerial Port Mode Mode Load Sbuf Baud Rates Smod Timer 1 generated commonly used Baud ratesMHZ JNB SINGLE-STEP OperationReti Kawasaki LSI USA Inc Global Serial Channel Introduction11/IDLE CRC None DC JAM CRCCsma Sdlc 11/IDLEExternal clock Internal clock Control cpu Control dma Raw Receive Raw Transmit CSMA/CD Frame Format CSMA/CD OverviewPreamble BOF Address Info CRC EOF Kawasaki LSI USA, Inc Ver .9 KS152JB2 23 24 Interframe Space Collision Detection CSMA/CD Data EncodingManchester Encoding BIT Time Jitter ToleranceMissing 0-to-1 Transition Narrow PulsesUnexpected 1-to-0 Transition Response to a Detected Collision What the GSC was doing Resolution of CollisionsGSC Inactive TfifoDCR BackoffAlgorithm Prbs Tcdcnt Load Bkoff Slot Clock Myslot Random BackoffBKOFF= Myslot Deterministic Backoff Hardware Based Acknowledge Kawasaki LSI USA, Inc Ver .9 KS152JB2 Sdlc Frame Format BOF Address Control Info CRC EOFKawasaki LSI USA, Inc Ver .9 KS152JB2 Nrzi BIT Time Data EncodingBIT STUFFING/STRIPPING Line Idle Sending Abort CharacterAcknowledgement Multi-Drop Network PRIMARY/SECONDARY StationsPoint-to-point Network Ring NetworkSdlc Hdlc Using a Preamble in SdlcHDLC/SDLC Comparison User Defined ProtocolsLine Discipline Planning for Network Changes and ExpansionsDMA Servicing of GSC Channels Kawasaki LSI USA, Inc Ver .9 KS152JB2 Baud Rate Initialization Test Modes External Driver InterfaceJitter Receive BIT Time Received Local Value Manchester Encoding BIT TimeReceive Sampling Rate Received Transmit WaveformsReceiver Clock Recovery CSMA/CD Clock RecoveryRcbat Crce Determining Receiver ErrorsExternal Clocking AddressingDetermining Line Discipline 2 CPU/DMA Control of the GSCCollisions and Backoff What the GSC was doing Response GSC Register Descriptions Successful Ending of Transmissions and ReceptionsGMOD84H Xtclk PL1 PL0 PL1 PL0 Length BitsKawasaki LSI USA, Inc Ver .9 KS152JB2 DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 ARB REQ Garen Xrclk Gfien IDLRcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc Ver .9 KS152JB2 LNI Noack Tcdt TDN Tfnf TEN DMA Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Operation DMA with the 80C152DMA Registers DAS IDA Alternate Cycle ModeBurst Mode SAS ISASerial Port Demand Mode External Demand ModePCH P2 SFR DMA Cycle Resume Program Execution Timing Diagrams12 OSC.PERIODS ALE Psen P1 Inst Float DMA Transfer from Internal Memory to Internal MemoryDMA Cycle 12 OSC. Periods Resume Program Execution ALE Psen 12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCHDMA Cycle Resume Program Execution Arbiter Mode Request ModeHold/Hold Acknowledge Using the HOLD/HLDA Acknowledge ARB REQInternal Logic of the Arbiter ALE ARB If Hlda = ALE AEQ ALE REQDmxrq Internal Logic of the Requester DMA Arbitration Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Arbitration with Hold/Hold Ack Summary of DMA Control Bits DAS IDA SAS ISA DoneInterrupt Structure IE0 TI+RI ET1 EX1 ET0 EX0PT1 PX1 PT0 PX0 IPN1GSC Transmitter Error Conditions Transmit Error Flags Logic for Clearing TEN, Setting TDNGSC Receiver Error Conditions Glossary Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCON0/1 092H,093H Xtclk PL1 PL0 Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2 PT1 PX1 PT0 EX0 Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Smod ARB REQ Garen Xrclk Gfien IDL OVR Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2 SM0 SM1 SM2 REN TB8 RB8 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0Gate Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2 Data Pointer LOW PortStack Pointer DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0 Timer ControlData Pointer High DPHTimer 0 LSB Timer Mode ControlGate Timer Timer 1 LSBTimer 0 MSB Timer 1 MSBSerial Data Buffer Serial Port ControlSM0 SBUF.7Program Status Word RS1 RS0Accumulator ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0Kawasaki LSI USA, Inc 119 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2
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