Kawasaki 80C51, KS152JB, 80C152 Determining Line Discipline, 2 CPU/DMA Control of the GSC

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KS152JB Universal Communications Controller Technical Specifications

to each station. When using 16-bit addressing, ADR0:ADR1 form one address and ADR2:ADR3 form the second address. If the receiver is enabled, it looks for a matching address after every BOF flag is detected. As the data is received, if the 8th (or 16th) bit does not match the address recognition circuitry, the rest of the frame is ignored and the search continues for another flag. if the address does match the address recognition circuitry, the address and all subsequent data is passed into the receive FIFO until the EOF flag or an error occurs. The address is not stripped and is also passed to RFIFO.

The address masking registers, AMSK0 and AMSK1, work in conjunction with ADR0 and ADR1 respectively to identify “don’t care” bits. A 1 in any position in the AMSKn register makes the respective bit in the ADRn register irrelevant. These combinations can then be used for form group addresses. If the masking registers are filled with all 1s, the C152 will receive all packets, which is called the promiscuous mode. If 16-bit addressing is used, AMSK0:AMSK1 form one 16-bit address mask.

3.6 GSC Operation

3.6.1 Determining Line Discipline

In normal operation the GSC uses full or half duplex operation. When using a 32-bit CRC (GMOD.3 = 1), operation can only be half duplex. If using a 16-bit CRC (GMOD.3 = 0), full duplex is selected by default. When using a 16-bit CRC the receiver can be turned off while trans- mitting (RSTAT.1 = 0), and the transmitter can be turned off during reception (TSTAT.1 = 0). This simulates half-duplex operation when using a 16-bit CRC.

Normally, HDLC uses a 16-bit CRC, so half duplex is determined by turning off the receiver or transmitter. This is so that the receiver will not detect its own address as transmission takes place. This also needs to be done when using CSMA/CD with a 16-bit CRC for the same reason.

3.6.2 CPU/DMA CONTROL OF THE GSC

The data for transmission or reception can be handled by either the CPU (TSTAT.0 = 0) or DMA controller (TSTAT.0 = 1). This allows the user two sets of flags to control the FIFO. Associated with these flags are interrupts, which may be enabled by the user software. Either one or both sets of flags may be used at the same time.

In CPU control mode the flags (RFNE, TFNF) are generated by the condition of the receive or transmit FIFO’s. After loading a byte into the transmit FIFO, there is a one machine cycle latency until the TFNF flag is updated. Because of this latency, the status of TFNF should not be checked immediately following the instruction to load the transmit FIFO. If using the interrupts to service the transmit FIFO, the one machine cycle of latency must be considered if the TFNF flag is checked prior to leaving the subroutine.

When using the CPU for control, transmission normally is initiated by setting TEN bit (TSTAT.1)

Kawasaki LSI USA, Inc.

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Ver. 0.9 KS152JB2

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Contents Introduction Technical Specifications PIN Description Pin DescriptionName Description Port Pin Name Alternate FunctionRST XTAL1XTAL2 Psen ALEEben EpsenSFR map for the cpu Special function RegistersReset Timing Reset Values of the SFRs Scon ConfigurationsSbuf Indeterminate Tmod PconPort bit I/O Pads Port 0 I/O Pad Port 2 I/O PadPorts 4,5 Psen Epsen ProgramComments Fetch viaTmod Timer/Counter Mode Control Register TIMER/COUNTERSMode Tcon Timer/Counter Control RegisterTimer/Counter in Mode Interrupts Timer/Counter 0 in ModeIE Interrupt Enable Register Priority Level Structure Pgste PDMA1 Pgstv PDMA0 Pgsre Pgsrv Egste EDMA1 Egstv EDMA0 Egsre EgsrvEX0 PX0Pgsrv Egsrv 2BHEDMA1 PDMA1PT1 ET1 1BHKawasaki LSI USA, Inc Ver .9 KS152JB2 ALE Psen Power Down and IdleStatus of the External Pins during Idle and Power Down Smod IDL Pcon Power Control RegisterLocal Serial Channel Controller Local Serial Port ModeSerial Port Mode Mode Load Sbuf Baud Rates MHZ Timer 1 generated commonly used Baud ratesSmod Reti SINGLE-STEP OperationJNB Kawasaki LSI USA Inc Introduction Global Serial ChannelDC JAM CRC 11/IDLE CRC None11/IDLE Csma SdlcExternal clock Internal clock Control cpu Control dma Raw Receive Raw Transmit Preamble BOF Address Info CRC EOF CSMA/CD OverviewCSMA/CD Frame Format Kawasaki LSI USA, Inc Ver .9 KS152JB2 23 24 Interframe Space Manchester Encoding BIT Time CSMA/CD Data EncodingCollision Detection Jitter ToleranceUnexpected 1-to-0 Transition Narrow PulsesMissing 0-to-1 Transition GSC Inactive Resolution of CollisionsResponse to a Detected Collision What the GSC was doing TfifoAlgorithm BackoffDCR BKOFF= Myslot Random BackoffPrbs Tcdcnt Load Bkoff Slot Clock Myslot Deterministic Backoff Hardware Based Acknowledge Kawasaki LSI USA, Inc Ver .9 KS152JB2 BOF Address Control Info CRC EOF Sdlc Frame FormatKawasaki LSI USA, Inc Ver .9 KS152JB2 BIT STUFFING/STRIPPING Data EncodingNrzi BIT Time Acknowledgement Sending Abort CharacterLine Idle Point-to-point Network PRIMARY/SECONDARY StationsMulti-Drop Network Ring NetworkHDLC/SDLC Comparison Using a Preamble in SdlcSdlc Hdlc User Defined ProtocolsPlanning for Network Changes and Expansions Line DisciplineDMA Servicing of GSC Channels Kawasaki LSI USA, Inc Ver .9 KS152JB2 Baud Rate Initialization External Driver Interface Test ModesJitter Receive Receive Sampling Rate Received Local Value Manchester Encoding BIT TimeBIT Time Received Transmit WaveformsCSMA/CD Clock Recovery Receiver Clock RecoveryExternal Clocking Determining Receiver ErrorsRcbat Crce Addressing2 CPU/DMA Control of the GSC Determining Line DisciplineCollisions and Backoff What the GSC was doing Response Successful Ending of Transmissions and Receptions GSC Register DescriptionsPL1 PL0 Length Bits GMOD84H Xtclk PL1 PL0Kawasaki LSI USA, Inc Ver .9 KS152JB2 ARB REQ Garen Xrclk Gfien IDL DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc Ver .9 KS152JB2 LNI Noack Tcdt TDN Tfnf TEN DMA Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA with the 80C152 DMA OperationDMA Registers Burst Mode Alternate Cycle ModeDAS IDA SAS ISAExternal Demand Mode Serial Port Demand Mode12 OSC.PERIODS ALE Psen P1 Inst Float Timing DiagramsPCH P2 SFR DMA Cycle Resume Program Execution DMA Transfer from Internal Memory to Internal MemoryDMA Cycle Resume Program Execution 12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCHDMA Cycle 12 OSC. Periods Resume Program Execution ALE Psen Hold/Hold Acknowledge Request ModeArbiter Mode ARB REQ Using the HOLD/HLDA AcknowledgeDmxrq ALE ARB If Hlda = ALE AEQ ALE REQInternal Logic of the Arbiter Internal Logic of the Requester DMA Arbitration Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Arbitration with Hold/Hold Ack DAS IDA SAS ISA Done Summary of DMA Control BitsInterrupt Structure IE0 ET1 EX1 ET0 EX0 TI+RIIPN1 PT1 PX1 PT0 PX0Transmit Error Flags Logic for Clearing TEN, Setting TDN GSC Transmitter Error ConditionsGSC Receiver Error Conditions Glossary Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCON0/1 092H,093H Xtclk PL1 PL0 Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2 PT1 PX1 PT0 EX0 Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Smod ARB REQ Garen Xrclk Gfien IDL OVR Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 SM0 SM1 SM2 REN TB8 RB8Gate Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2 Stack Pointer PortData Pointer LOW DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0Data Pointer High Timer ControlDPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0 DPHGate Timer Timer Mode ControlTimer 0 LSB Timer 1 LSBTimer 1 MSB Timer 0 MSBSM0 Serial Port ControlSerial Data Buffer SBUF.7RS1 RS0 Program Status WordACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 AccumulatorKawasaki LSI USA, Inc 119 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2
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