Kawasaki 80C51, KS152JB, 80C152 technical specifications Ale, Psen, Eben, Epsen

Page 5

KS152JB Universal Communications Controller Technical Specifications

 

 

 

 

 

 

 

 

Table 1: PIN DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address Latch Enable output signal for latching the low byte of the address during

 

ALE

 

 

 

 

 

 

 

accesses to external memory.

 

 

 

 

 

 

 

In normal operation ALE is emitted at a constant rate of 1/6 the oscillator fre-

 

 

 

 

 

 

 

quency, and may be used for external timing or clocking purposes. Note, however,

 

 

 

 

 

 

 

that one ALE pulse is skipped during each access to external Data Memory. While

 

 

 

 

 

 

 

in Reset, ALE remains at a constant high level.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Program Store Enable is the Read strobe to External Program Memory. When the

 

PSEN

 

 

 

 

 

 

 

8XC152 is executing from external program memory,

 

 

is active (low). When

 

 

 

 

 

 

 

PSEN

 

 

 

 

 

 

 

the device is executing code from External Program Memory,

PSEN

is activated

 

 

 

 

 

 

 

twice each machine cycle, except that two

 

 

activations are skipped during

 

 

 

 

 

 

 

PSEN

 

 

 

 

 

 

 

each access to External Data Memory. While in Reset,

 

 

remains at a con-

 

 

 

 

 

 

 

PSEN

 

 

 

 

 

 

 

stant high level.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

External Access enable.

 

 

must be externally pulled low in order to enable the

 

EA

EA

 

 

 

 

 

 

 

8XC152 to fetch code from External Program Memory locations 0000H to

 

 

 

 

 

 

 

0FFFH.

 

 

 

 

 

 

 

 

must be connected to VCC for internal program execution.

 

 

 

 

 

 

 

EA

 

EBEN

 

E-Bus Enable input that designates whether program memory fetches take place

 

 

 

 

 

 

 

via Ports 0 and 2 or ports 5 and 6. Table 2.1 shows how the ports are used in con-

 

 

 

 

 

 

 

junction with EBEN.

 

 

 

 

 

 

 

 

 

 

 

 

E-bus program Store Enable is the Read strobe to external program memory when

 

EPSEN

 

 

 

 

 

 

 

EBEN is high. Table 2.1 shows when

EPSEN

is used relative to

PSEN

depending

 

 

 

 

 

 

 

on the status of EBEN and

 

 

 

 

 

 

 

 

 

EA.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Kawasaki LSI USA, Inc.

Page 5 of 120

Ver. 0.9 KS152JB2

Image 5
Contents Introduction Technical Specifications PIN Description Pin DescriptionName Description Port Pin Name Alternate FunctionRST XTAL1XTAL2 Psen ALEEben EpsenSFR map for the cpu Special function RegistersReset Timing Reset Values of the SFRs Scon ConfigurationsSbuf Indeterminate Tmod PconPort bit I/O Pads Port 0 I/O Pad Port 2 I/O PadPorts 4,5 Psen Epsen ProgramComments Fetch viaTmod Timer/Counter Mode Control Register TIMER/COUNTERSMode Tcon Timer/Counter Control RegisterTimer/Counter in Mode Interrupts Timer/Counter 0 in ModeIE Interrupt Enable Register Priority Level Structure Pgste PDMA1 Pgstv PDMA0 Pgsre Pgsrv Egste EDMA1 Egstv EDMA0 Egsre EgsrvEX0 PX0Pgsrv Egsrv 2BHEDMA1 PDMA1PT1 ET1 1BHKawasaki LSI USA, Inc Ver .9 KS152JB2 ALE Psen Power Down and IdleStatus of the External Pins during Idle and Power Down Smod IDL Pcon Power Control RegisterLocal Serial Channel Controller Local Serial Port ModeSerial Port Mode Mode Load Sbuf Baud Rates MHZ Timer 1 generated commonly used Baud ratesSmod Reti SINGLE-STEP OperationJNB Kawasaki LSI USA Inc Introduction Global Serial ChannelDC JAM CRC 11/IDLE CRC None11/IDLE Csma SdlcExternal clock Internal clock Control cpu Control dma Raw Receive Raw Transmit Preamble BOF Address Info CRC EOF CSMA/CD OverviewCSMA/CD Frame Format Kawasaki LSI USA, Inc Ver .9 KS152JB2 23 24 Interframe Space Manchester Encoding BIT Time CSMA/CD Data EncodingCollision Detection Jitter ToleranceUnexpected 1-to-0 Transition Narrow PulsesMissing 0-to-1 Transition GSC Inactive Resolution of CollisionsResponse to a Detected Collision What the GSC was doing TfifoAlgorithm BackoffDCR BKOFF= Myslot Random BackoffPrbs Tcdcnt Load Bkoff Slot Clock Myslot Deterministic Backoff Hardware Based Acknowledge Kawasaki LSI USA, Inc Ver .9 KS152JB2 BOF Address Control Info CRC EOF Sdlc Frame FormatKawasaki LSI USA, Inc Ver .9 KS152JB2 BIT STUFFING/STRIPPING Data EncodingNrzi BIT Time Acknowledgement Sending Abort CharacterLine Idle Point-to-point Network PRIMARY/SECONDARY StationsMulti-Drop Network Ring NetworkHDLC/SDLC Comparison Using a Preamble in SdlcSdlc Hdlc User Defined ProtocolsPlanning for Network Changes and Expansions Line DisciplineDMA Servicing of GSC Channels Kawasaki LSI USA, Inc Ver .9 KS152JB2 Baud Rate Initialization External Driver Interface Test ModesJitter Receive Receive Sampling Rate Received Local Value Manchester Encoding BIT TimeBIT Time Received Transmit WaveformsCSMA/CD Clock Recovery Receiver Clock RecoveryExternal Clocking Determining Receiver ErrorsRcbat Crce Addressing2 CPU/DMA Control of the GSC Determining Line DisciplineCollisions and Backoff What the GSC was doing Response Successful Ending of Transmissions and Receptions GSC Register DescriptionsPL1 PL0 Length Bits GMOD84H Xtclk PL1 PL0Kawasaki LSI USA, Inc Ver .9 KS152JB2 ARB REQ Garen Xrclk Gfien IDL DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc Ver .9 KS152JB2 LNI Noack Tcdt TDN Tfnf TEN DMA Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA with the 80C152 DMA OperationDMA Registers Burst Mode Alternate Cycle ModeDAS IDA SAS ISAExternal Demand Mode Serial Port Demand Mode12 OSC.PERIODS ALE Psen P1 Inst Float Timing DiagramsPCH P2 SFR DMA Cycle Resume Program Execution DMA Transfer from Internal Memory to Internal MemoryDMA Cycle Resume Program Execution 12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCHDMA Cycle 12 OSC. Periods Resume Program Execution ALE Psen Hold/Hold Acknowledge Request ModeArbiter Mode ARB REQ Using the HOLD/HLDA AcknowledgeDmxrq ALE ARB If Hlda = ALE AEQ ALE REQInternal Logic of the Arbiter Internal Logic of the Requester DMA Arbitration Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Arbitration with Hold/Hold Ack DAS IDA SAS ISA Done Summary of DMA Control BitsInterrupt Structure IE0 ET1 EX1 ET0 EX0 TI+RIIPN1 PT1 PX1 PT0 PX0Transmit Error Flags Logic for Clearing TEN, Setting TDN GSC Transmitter Error ConditionsGSC Receiver Error Conditions Glossary Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCON0/1 092H,093H Xtclk PL1 PL0 Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2 PT1 PX1 PT0 EX0 Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Smod ARB REQ Garen Xrclk Gfien IDL OVR Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 SM0 SM1 SM2 REN TB8 RB8Gate Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2 Stack Pointer PortData Pointer LOW DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0Data Pointer High Timer ControlDPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0 DPHGate Timer Timer Mode ControlTimer 0 LSB Timer 1 LSBTimer 1 MSB Timer 0 MSBSM0 Serial Port ControlSerial Data Buffer SBUF.7RS1 RS0 Program Status WordACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 AccumulatorKawasaki LSI USA, Inc 119 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2