Spectrum Brands MI.61XX manual Hardware information, Block diagram Technical Data

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Introduction	Hardware information

Hardware information

Block diagram

Technical Data

Resolution	8	Bit	Dimension	312 mm x 107 mm
Integral linearity (DAC)	± 1.5 LSB typ.		Width (Standard)	1 full size slot
Differential linearity (DAC)	± 1.0 LSB typ.		Width (with star hub option)	2 full size slots
Output resistance	< 1 Ohm		Analogue connector	3 mm SMB male
Max output swing in 50 Ohm	± 3 V (offset + amplitude)		Warm up time	10 minutes
Max slew rate (no filter)	> 0.9 V/ns		Operating temperature	0°C - 50°C
Multi: Trigger to 1st sample delay	fixed		Storage temperature	-10°C - 70°C
Multi: Recovery time	< 20 samples		Humidity	10% to 90%
Ext. clock: delay to internal clock	42 ns ± 2 ns		Offset stepsize	< 2 mV
Trigger output delay	1 Sample		Amplitude stepsize	< 1 mV
Crosstalk @ 1 MHz signal ±3 V	< -80 dB
Min internal clock	1 kS/s		Power consumption 5 V @ full speed	max 3.7 A (18.5 Watt)
Min external clock	DC		Power consumption 5 V @ power down	max 2.3 A (11.5 Watt)

	MI.6110	MI.6111
max internal clock	125 MS/s	125 MS/s
max external clock	125 MS/s	125 MS/s
-3 dB bandwidth no filter	> 60 MHz	> 60 MHz

(c) Spectrum GmbH

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Contents English version October 5 MI.61xxPage Software Hardware InstallationSoftware Driver Installation IntroductionStandard generation modes Fifo ModeProgramming the Board Analog OutputsAppendix Option Gated ReplayOption Extra I/O Synchronization OptionPreface IntroductionPreface General InformationIntroduction Different models of the MI.61xx seriesMI.6110 MI.6111 Extra I/O Option -XIO Additional optionsExtra I/O Option -XMF Introduction Additional options StarhubSpectrum type plate Hardware information Block diagram Technical DataFilter Dynamic ParametersOrder information Hardware informationIntroductionSystem Requirements Hardware InstallationInstalling the board in the system Installing a board with extra I/O Option -XMF Installing a board with digital inputs/outputsOnly use the included flat ribbon cables Installing multiple boards synchronized by starhubMounting the wired boards Hooking up the boardsInstalling multiple synchronized boards Interrupt Sharing Software Driver InstallationSoftware Driver Installation Version control InstallationWindows Driver Update Windows Software Driver Installation Windows Windows XP Windows XP Adding boards to the Windows NT driver Windows NTOverview LinuxAutomatic load of the driver Installing the deviceNow it is possible to access the board using this device Driver infoSoftware SoftwareSoftware Overview First Test with SBenchLinux Gnu C ++ Driver InterfaceHeader files Microsoft Visual C++Include Drivers Other Windows C/C++ compilersNational Instruments LabWindows/CVI Driver functionsFunction SpcGetData Function SpcSetParamFunction SpcSetParam Function SpcSetData WindowsSpectrum GmbH Examples Delphi Pascal Programming InterfaceType definition Include DriverDelphi Pascal Programming Interface VBA for Excel Examples Visual Basic Programming InterfaceVisual Basic Examples Visual Basic Programming Interface Register tables Error handlingProgramming the Board OverviewPCI Register Example for error checkingInitialization Starting the automatic initialization routineSerial number Installed memoryHardware version Date of productionDriver version Installed features and optionsUsed interrupt line Used type of driverSpcpciserialno Powerdown and resetExample program for the board initialization SpcpcimemsizeDisabling the outputs Analog OutputsChannel Selection Important note on channels selectionRegister Value Direction Description Amplitude range Setting up the outputsOutput Amplifiers Output offsetOutput Filters Filter SpecificationsMaximum Output Range Programming Standard generation modesGeneral description Minimum and stepsize of memsize and posttrigger in samples Standard generation modes ProgrammingMaximum memsize Maximum posttrigger in MSamplesProgrammingStandard generation modes Starting without interrupt classic modeStarting with interrupt driven mode Command registerValue ’len’ as a 32 bit integer value Data organizationWriting data with SpcSetData Value ’start’ as a 32 bit integer valueSample format Standard modeBit Standard Mode Speed Limitations Fifo ModeGeneral Information Background Fifo Write60040 Read out the number of available Fifo buffers Programming Fifo ModeSoftware Buffers Theoretical maximum sample rate PCI Bus ThroughputDigital I/O 701x or 702x or pattern generator boards Fifo Mode ProgrammingBuffer processing Analog acquisition or generation boardsSpcfifowait Example Fifo generation mode== Maxbuf SpcfifostartProgramming Standard internal sample rate Clock generationInternally generated sample rate External clocking Using plain quartz with no PLLExternal reference clock Maximum external samplerate in MS/s Direct external clockMinimum external sample rate CHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 External clock with dividerExample External TTL trigger Example for setting up the software triggerTrigger modes and appendant registers Software triggerPositive TTL trigger Example on how to set up the board for positive TTL triggerEdge triggers Trigger modes and appendant registersPositive and negative TTL trigger Trigger modes Standard ModeOption Multiple Replay Output modesTrigger modes Option Multiple Replay Resulting start delaysValue Direction Description General information and trigger delayOption Gated Replay Option Gated ReplaySpctriggermode Tmttlpos Example programAllowed trigger modes External TTL edge triggerTransfer Data Option Extra I/ODigital I/Os Channel directionAnalog Outputs Option Extra I/O Analog OutputsProgramming example Synchronization with option starhub Synchronization OptionDifferent synchronization options Synchronization with option cascadingWrite Data to on-board memory output boards only Setup order for the different synchronization optionsSet up the board parameters Example of board setup for three boardsDefine the remaining boards as trigger slaves Define the boards for trigger masterExample of board #2 set as trigger master 3a Define synchronization or triggerArm the boards for synchronization Define the board for clock masterExample board number 0 is clock master Define the remaining boards as clock slavesExample for data reading Start all of the trigger master boardsWait for the end of the measurement Read data from the on-board memory acquisition boards onlySpcsyncslavefifo Allocate the Fifo software buffers2a Write first data for output boards SpcsyncmasterfifoAs trigger slaves 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx Additions for synchronizing different boardsGeneral information Calculating the clock dividersBoard type 3025 3131 Setting up the clock dividerBoard type 3122 3120 40 MS/sAdditions for equal boards with different sample rates Resulting delays using different boards or speedsDelay in standard non Fifo modes Delay in Fifo modeAppendix Error CodesError name Value hex Value dec Error description AppendixPin assignment of the multipin cable Pin assignment of the multipin connectorExtra I/O with external connectorOption -XMF D15 D13 D11 Pin assignment of the internal multipin connectorExtra I/O with internal connector Option -XIO D14 D12 D10