Spectrum Brands MI.61XX manual Software Buffers, Programming Fifo Mode

Page 50

Programming

FIFO Mode

 

 

 

 

Theoretical maximum sample rate

PCI Bus Throughput

1

Channel

100 MS/s

[1 Channel] x [1 Byte per sample] * 100 MS/s = 100 MB/s

2

Channels

50 MS/s

[2 Channels] x [1 Byte per sample] * 50 MS/s = 100 MB/s

4

Channels

25 MS/s

[4 Channels] x [1 Byte per sample] * 25 MS/s = 100 MB/s

8

Channels

12.5 MS/s

[8 Channels] x [1 Byte per sample] * 12.5 MS/s = 100 MB/s

When using FIFO mode together with one of the options that allow to have gaps in the generation like Multiple Replay or Gated Replay one can even run the board with higher sample rates. It just has to be sure that the average sample rate (calculated with generation time and gap) does not exceed the above mentioned sample rate limitations.

The sample rate that can be run in one of these mode is depending on the number of channels that have been activated. Due to the internal structure of the board this is limited to a internal throughput of 250 MB/s (250 MS/s):

 

 

Maximum sample rate that can be programmed

Internal throughput

1

Channel

250 MS/s

[1 Channel] x [1 Byte per sample] x 250 MS/s = 250 MB/s

2

Channels

125 MS/s

[2 Channels] x [1 Byte per sample] x 125 MS/s = 250 MB/s

4

Channels

62.5 MS/s

[4 Channels] x [1 Byte per sample] x 62.5 MS/s = 250 MB/s

8

Channels

31.25 MS/s

[8 Channels] x [1 Byte per sample] x 31.25 MS/s = 250 MB/s

Programming

The setup of FIFO mode is done with a few additional software registers described in this chapter. All the other settings can be used as des- cribed before. In FIFO mode the register SPC_MEMSIZE and SPC_POSTTRIGGER are not used.

Software Buffers

This register defines the number of software buffers that should be used for FIFO mode. The number of hardware buffers is always two and can not be changed by software.

Register

Value

Direction

Description

SPC_FIFO_BUFFERS

60000

r/w

Number of software buffers to be used for FIFO mode. Value has to be between 2 and 256

When this manual was printed there are a total of 256 buffers possible. However if there are changes and enhancements to the driver in the future it will be informative to read out the number of buffers the new driver version can hold.

Register

Value

Direction

Description

SPC_FIFO_BUFADRCNT

60040

r

Read out the number of available FIFO buffers

The length of each buffer is defined in bytes. This length is used for hardware and software buffers as well. Both have the same length. The maximum length that can be used is depending on the installed on-board memory.

Register

Value

Direction

Description

SPC_FIFO_BUFLEN

60010

r/w

Length of each buffer in bytes. Must be a multiple of 1024 bytes.

Each FIFO buffer can be a maximum of half the memory. Be aware that the buffer length is given in overall bytes not in samples. Therefore the value has to be calculated depending on the activated channels and the resolution of the board:

50

MI.61xx Manual

Page 49 Page 51
Image 50
Page 49 Page 51
Contents MI.61xx English version October 5Page Introduction Hardware InstallationSoftware Driver Installation SoftwareAnalog Outputs Fifo ModeProgramming the Board Standard generation modesSynchronization Option Option Gated ReplayOption Extra I/O AppendixGeneral Information IntroductionPreface PrefaceIntroduction Different models of the MI.61xx seriesMI.6110 MI.6111 Extra I/O Option -XIO Additional optionsExtra I/O Option -XMF Starhub Introduction Additional optionsSpectrum type plate Block diagram Technical Data Hardware informationHardware informationIntroduction Dynamic ParametersOrder information FilterSystem Requirements Hardware InstallationInstalling the board in the system Installing a board with digital inputs/outputs Installing a board with extra I/O Option -XMFHooking up the boards Installing multiple boards synchronized by starhubMounting the wired boards Only use the included flat ribbon cablesInstalling multiple synchronized boards Interrupt Sharing Software Driver InstallationSoftware Driver Installation Version control InstallationWindows Driver Update Windows Software Driver Installation Windows Windows XP Windows XP Windows NT Adding boards to the Windows NT driverLinux OverviewDriver info Installing the deviceNow it is possible to access the board using this device Automatic load of the driverFirst Test with SBench SoftwareSoftware Overview SoftwareMicrosoft Visual C++ ++ Driver InterfaceHeader files Linux Gnu CDriver functions Other Windows C/C++ compilersNational Instruments LabWindows/CVI Include DriversFunction SpcSetData Windows Function SpcSetParamFunction SpcSetParam Function SpcGetDataSpectrum GmbH Include Driver Delphi Pascal Programming InterfaceType definition ExamplesDelphi Pascal Programming Interface VBA for Excel Examples Visual Basic Programming InterfaceVisual Basic Examples Visual Basic Programming Interface Overview Error handlingProgramming the Board Register tablesStarting the automatic initialization routine Example for error checkingInitialization PCI RegisterDate of production Installed memoryHardware version Serial numberUsed type of driver Installed features and optionsUsed interrupt line Driver versionSpcpcimemsize Powerdown and resetExample program for the board initialization SpcpciserialnoImportant note on channels selection Analog OutputsChannel Selection Disabling the outputsOutput offset Setting up the outputsOutput Amplifiers Register Value Direction Description Amplitude rangeOutput Filters Filter SpecificationsMaximum Output Range Programming Standard generation modesGeneral description Maximum posttrigger in MSamples Standard generation modes ProgrammingMaximum memsize Minimum and stepsize of memsize and posttrigger in samplesCommand register Starting without interrupt classic modeStarting with interrupt driven mode ProgrammingStandard generation modesValue ’start’ as a 32 bit integer value Data organizationWriting data with SpcSetData Value ’len’ as a 32 bit integer valueSample format Standard modeBit Standard Mode Background Fifo Write Fifo ModeGeneral Information Speed LimitationsTheoretical maximum sample rate PCI Bus Throughput Programming Fifo ModeSoftware Buffers 60040 Read out the number of available Fifo buffersAnalog acquisition or generation boards Fifo Mode ProgrammingBuffer processing Digital I/O 701x or 702x or pattern generator boardsSpcfifostart Example Fifo generation mode== Maxbuf SpcfifowaitProgramming Standard internal sample rate Clock generationInternally generated sample rate External clocking Using plain quartz with no PLLExternal reference clock Maximum external samplerate in MS/s Direct external clockMinimum external sample rate CHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 External clock with dividerExample Software trigger Example for setting up the software triggerTrigger modes and appendant registers External TTL triggerTrigger modes and appendant registers Example on how to set up the board for positive TTL triggerEdge triggers Positive TTL triggerPositive and negative TTL trigger Output modes Standard ModeOption Multiple Replay Trigger modesResulting start delays Trigger modes Option Multiple ReplayOption Gated Replay General information and trigger delayOption Gated Replay Value Direction DescriptionExternal TTL edge trigger Example programAllowed trigger modes Spctriggermode TmttlposChannel direction Option Extra I/ODigital I/Os Transfer DataAnalog Outputs Option Extra I/O Analog OutputsProgramming example Synchronization with option cascading Synchronization OptionDifferent synchronization options Synchronization with option starhubExample of board setup for three boards Setup order for the different synchronization optionsSet up the board parameters Write Data to on-board memory output boards only3a Define synchronization or trigger Define the boards for trigger masterExample of board #2 set as trigger master Define the remaining boards as trigger slavesDefine the remaining boards as clock slaves Define the board for clock masterExample board number 0 is clock master Arm the boards for synchronizationRead data from the on-board memory acquisition boards only Start all of the trigger master boardsWait for the end of the measurement Example for data readingSpcsyncmasterfifo Allocate the Fifo software buffers2a Write first data for output boards SpcsyncslavefifoAs trigger slaves Calculating the clock dividers Additions for synchronizing different boardsGeneral information 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx40 MS/s Setting up the clock dividerBoard type 3122 3120 Board type 3025 3131Delay in Fifo mode Resulting delays using different boards or speedsDelay in standard non Fifo modes Additions for equal boards with different sample ratesAppendix Error CodesError name Value hex Value dec Error description AppendixPin assignment of the multipin cable Pin assignment of the multipin connectorExtra I/O with external connectorOption -XMF D14 D12 D10 Pin assignment of the internal multipin connectorExtra I/O with internal connector Option -XIO D15 D13 D11
Top Page Image Contents