Spectrum Brands MI.61XX Dynamic Parameters, Order information, Hardware informationIntroduction

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Hardware informationIntroduction

Dynamic Parameters

	MI.6110	MI.6111
Test - Samplerate	125 MS/s	125 MS/s
Filter 3
Characteristics	5th order Butterworth
-3 dB bandwidth	25 MHz	25 MHz
SNR ±1 V in 50 ohm	-49 dB
THD ±1 V in 50 ohm	-42 dB
Filter 2
Characteristics	4th order Butterworth
-3 dB bandwidth	5 MHz	5 MHz
SNR ±1 V in 50 ohm	-42 dB
THD ±1 V in 50 ohm	-67 dB
Filter 1
Characteristics	4th order Butterworth
-3 dB bandwidth	500 kHz	500 kHz
SNR ±1 V in 50 ohm	-72 dB
THD ±1 V in 50 ohm	-54 dB

Dynamic parameters are measured at ± 1 V output level and 50 Ohm termination with a spectrum analyser. The samplerate selected is the maximum possible samplerate. Signal fre- quency is equal to the cut-off frequency of the filter. SNR and RMS noise parameters may differ depending on the quality of the used PC. SNR = Signal to Noise Ratio, THD = Total Harmo- nic Distortion

Order information

Order No	Description		Order No	Description
MI6110	MI.6111 with 16 MSample memory and drivers/SBench 5.x		MI61xx-32M	Option: 32 MSample mem instead of 16 MSample standard mem
MI6111	MI.6111 with 16 MSample memory and drivers/SBench 5.x		MI61xx-64M	Option: 64 MSample mem instead of 16 MSample standard mem
			MI61xx-128M	Option: 128 MSample mem instead of 16 MSample standard mem
MI6xxx-mr	Option Multiple Replay: Memory segmentation		MI61xx-256M	Option: 256 MSample mem instead of 16 MSample standard mem
MI6xxx-gs	Option Gated Sampling: Gate signal controls replay		MI61xx-512M	Option: 512 MSample mem instead of 16 MSample standard mem
MI6xxx-cs	Synchronisation of 2 - 4 boards, one option per system		MI61xx-up	Additional handling costs for later memory upgrade
MI6xxx-smod	Star Hub: Synchronisation of 2 - 16 boards, one option per system		MI61xx-dl	DASYLab driver for MI.61xx series
MIxxxx.xio	Extra I/O, internal connector: 16 DI/O, 4 Analog out		MI61xx-hp	VEE driver for MI.61xx series
MIxxxx-xmf	Extra I/O, external connector: 24 DI/O, 4 Analog out, incl. cable		MI61xx-lv	LabVIEW driver for MI.61xx series
			MATLAB	MATLAB driver for all MI.xxxx, MC.xxxx and MX.xxxx series.
Cab-3f-9m-80	Adapter cable: SMB female to BNC male 80 cm		Cab-3f-9f-80	Adapter cable: SMB female to BNC female 80 cm
Cab-3f-9m-200	Adapter cable: SMB female to BNC male 200 cm		Cab-3f-9f-200	Adapter cable: SMB female to BNC female 200 cm

12	MI.61xx Manual

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Contents MI.61xx English version October 5Page Hardware Installation Software Driver InstallationIntroduction SoftwareFifo Mode Programming the BoardAnalog Outputs Standard generation modesOption Gated Replay Option Extra I/OSynchronization Option AppendixIntroduction PrefaceGeneral Information PrefaceDifferent models of the MI.61xx series MI.6110 MI.6111Introduction Additional options Extra I/O Option -XMFExtra I/O Option -XIO Starhub Introduction Additional optionsSpectrum type plate Block diagram Technical Data Hardware informationDynamic Parameters Order informationHardware informationIntroduction FilterHardware Installation Installing the board in the systemSystem Requirements Installing a board with digital inputs/outputs Installing a board with extra I/O Option -XMFInstalling multiple boards synchronized by starhub Mounting the wired boardsHooking up the boards Only use the included flat ribbon cablesInstalling multiple synchronized boards Software Driver Installation Software Driver InstallationInterrupt Sharing Installation WindowsVersion control Driver Update Windows Software Driver Installation Windows Windows XP Windows XP Windows NT Adding boards to the Windows NT driverLinux OverviewInstalling the device Now it is possible to access the board using this deviceDriver info Automatic load of the driverSoftware Software OverviewFirst Test with SBench Software++ Driver Interface Header filesMicrosoft Visual C++ Linux Gnu COther Windows C/C++ compilers National Instruments LabWindows/CVIDriver functions Include DriversFunction SpcSetParam Function SpcSetParamFunction SpcSetData Windows Function SpcGetDataSpectrum GmbH Delphi Pascal Programming Interface Type definitionInclude Driver ExamplesDelphi Pascal Programming Interface Visual Basic Programming Interface Visual Basic ExamplesVBA for Excel Examples Visual Basic Programming Interface Error handling Programming the BoardOverview Register tablesExample for error checking InitializationStarting the automatic initialization routine PCI RegisterInstalled memory Hardware versionDate of production Serial numberInstalled features and options Used interrupt lineUsed type of driver Driver versionPowerdown and reset Example program for the board initializationSpcpcimemsize SpcpciserialnoAnalog Outputs Channel SelectionImportant note on channels selection Disabling the outputsSetting up the outputs Output AmplifiersOutput offset Register Value Direction Description Amplitude rangeFilter Specifications Maximum Output RangeOutput Filters Standard generation modes General descriptionProgramming Standard generation modes Programming Maximum memsizeMaximum posttrigger in MSamples Minimum and stepsize of memsize and posttrigger in samplesStarting without interrupt classic mode Starting with interrupt driven modeCommand register ProgrammingStandard generation modesData organization Writing data with SpcSetDataValue ’start’ as a 32 bit integer value Value ’len’ as a 32 bit integer valueStandard mode Bit Standard ModeSample format Fifo Mode General InformationBackground Fifo Write Speed LimitationsProgramming Fifo Mode Software BuffersTheoretical maximum sample rate PCI Bus Throughput 60040 Read out the number of available Fifo buffersFifo Mode Programming Buffer processingAnalog acquisition or generation boards Digital I/O 701x or 702x or pattern generator boardsExample Fifo generation mode == MaxbufSpcfifostart SpcfifowaitProgramming Clock generation Internally generated sample rateStandard internal sample rate Using plain quartz with no PLL External reference clockExternal clocking Direct external clock Minimum external sample rateMaximum external samplerate in MS/s External clock with divider ExampleCHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 Example for setting up the software trigger Trigger modes and appendant registersSoftware trigger External TTL triggerExample on how to set up the board for positive TTL trigger Edge triggersTrigger modes and appendant registers Positive TTL triggerPositive and negative TTL trigger Standard Mode Option Multiple ReplayOutput modes Trigger modesResulting start delays Trigger modes Option Multiple ReplayGeneral information and trigger delay Option Gated ReplayOption Gated Replay Value Direction DescriptionExample program Allowed trigger modesExternal TTL edge trigger Spctriggermode TmttlposOption Extra I/O Digital I/OsChannel direction Transfer DataAnalog Outputs Programming exampleAnalog Outputs Option Extra I/O Synchronization Option Different synchronization optionsSynchronization with option cascading Synchronization with option starhubSetup order for the different synchronization options Set up the board parametersExample of board setup for three boards Write Data to on-board memory output boards onlyDefine the boards for trigger master Example of board #2 set as trigger master3a Define synchronization or trigger Define the remaining boards as trigger slavesDefine the board for clock master Example board number 0 is clock masterDefine the remaining boards as clock slaves Arm the boards for synchronizationStart all of the trigger master boards Wait for the end of the measurementRead data from the on-board memory acquisition boards only Example for data readingAllocate the Fifo software buffers 2a Write first data for output boardsSpcsyncmasterfifo SpcsyncslavefifoAs trigger slaves Additions for synchronizing different boards General informationCalculating the clock dividers 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xxSetting up the clock divider Board type 3122 312040 MS/s Board type 3025 3131Resulting delays using different boards or speeds Delay in standard non Fifo modesDelay in Fifo mode Additions for equal boards with different sample ratesError Codes Error name Value hex Value dec Error descriptionAppendix AppendixPin assignment of the multipin connector Extra I/O with external connectorOption -XMFPin assignment of the multipin cable Pin assignment of the internal multipin connector Extra I/O with internal connector Option -XIOD14 D12 D10 D15 D13 D11