Spectrum Brands MI.61XX manual Option Gated Replay, General information and trigger delay

Page 63

Option Gated Replay

Output modes

 

 

Option Gated Replay

The option Gated Replay allows the data generation controlled by an external gate signal. Data will only be output, if the programmed gate condition is true.

Output modes

Standard Mode

Data will be replayed as long as the gate signal fulfills the gate condition that has had to be programmed before. At the end of the gate interval the replay will be stopped and the board will pause until another gates condition is detected. If the total amount of data to replay has been reached the board stops im- mediately (see figure). The total amount of samples to be replay- ed can be defined by the memsize register.

The table below shows the register for enabling Gated Replay. For detailed information on how to setup and start the standard generation mode please refer to the relevant chapter earlier in this manual.

Register

SPC_GATE

SPC_MEMSIZE

Value

Direction

Description

220400

r/w

Enables Gated Replay mode.

10000

r/w

Defines the total amount of samples to replay.

 

 

 

FIFO Mode

The Gated Replay in FIFO Mode is similar to the Gated Replay in Standard Mode. In contrast to the Standard mode you cannot program a certain total amount of samples to be replayed. The generation is running until the user stops it. The data is transfered to the board FIFO block by FIFO block by the driver. These blocks can be online generated by the user program.

The advantage of Gated Replay in FIFO mode is that you can stream data online from the host system to the board, so you can replay a huge amount of data from the hard disk with a lower average data rate than in conventional FIFO mode. The table be- low shows the dedicated register for enabling Gated Replay. For

detailed information how to setup and start the board in FIFO mode please refer to the according chapter earlier in this manual.

Register

SPC_GATE

Value

Direction

Description

220400

r/w

Enables Gated Replay mode.

 

 

 

Trigger modes

General information and trigger delay

Not all of the board’s trigger modes can be used in combi- nation with Gated Replay. All possible trigger modes are li- sted below. Depending on the different trigger modes, the chosen sample rate, the used channels and activated board synchronization (see according chapter for details about synchronizing multiple boards) there are different delay times between the trigger event and the first replayed sam- ple(see figure). This start delay is necessary as the board is equipped with dynamic RAM, which needs refresh cycles to keep the data in memory when the board is not replaying. It is fix for a certain board setup.

All possible start delays in samples between the trigger event and the first replayed sample are listed in the table below.

(c) Spectrum GmbH

63

Page 62 Page 64
Image 63
Page 62 Page 64
Contents English version October 5 MI.61xxPage Software Hardware InstallationSoftware Driver Installation IntroductionStandard generation modes Fifo ModeProgramming the Board Analog OutputsAppendix Option Gated ReplayOption Extra I/O Synchronization OptionPreface IntroductionPreface General InformationDifferent models of the MI.61xx series MI.6110 MI.6111Introduction Additional options Extra I/O Option -XMFExtra I/O Option -XIO Introduction Additional options StarhubSpectrum type plate Hardware information Block diagram Technical DataFilter Dynamic ParametersOrder information Hardware informationIntroductionHardware Installation Installing the board in the systemSystem Requirements Installing a board with extra I/O Option -XMF Installing a board with digital inputs/outputsOnly use the included flat ribbon cables Installing multiple boards synchronized by starhubMounting the wired boards Hooking up the boardsInstalling multiple synchronized boards Software Driver Installation Software Driver InstallationInterrupt Sharing Installation WindowsVersion control Driver Update Windows Software Driver Installation Windows Windows XP Windows XP Adding boards to the Windows NT driver Windows NTOverview LinuxAutomatic load of the driver Installing the deviceNow it is possible to access the board using this device Driver infoSoftware SoftwareSoftware Overview First Test with SBenchLinux Gnu C ++ Driver InterfaceHeader files Microsoft Visual C++Include Drivers Other Windows C/C++ compilersNational Instruments LabWindows/CVI Driver functionsFunction SpcGetData Function SpcSetParamFunction SpcSetParam Function SpcSetData WindowsSpectrum GmbH Examples Delphi Pascal Programming InterfaceType definition Include DriverDelphi Pascal Programming Interface Visual Basic Programming Interface Visual Basic ExamplesVBA for Excel Examples Visual Basic Programming Interface Register tables Error handlingProgramming the Board OverviewPCI Register Example for error checkingInitialization Starting the automatic initialization routineSerial number Installed memoryHardware version Date of productionDriver version Installed features and optionsUsed interrupt line Used type of driverSpcpciserialno Powerdown and resetExample program for the board initialization SpcpcimemsizeDisabling the outputs Analog OutputsChannel Selection Important note on channels selectionRegister Value Direction Description Amplitude range Setting up the outputsOutput Amplifiers Output offsetFilter Specifications Maximum Output RangeOutput Filters Standard generation modes General descriptionProgramming Minimum and stepsize of memsize and posttrigger in samples Standard generation modes ProgrammingMaximum memsize Maximum posttrigger in MSamplesProgrammingStandard generation modes Starting without interrupt classic modeStarting with interrupt driven mode Command registerValue ’len’ as a 32 bit integer value Data organizationWriting data with SpcSetData Value ’start’ as a 32 bit integer valueStandard mode Bit Standard ModeSample format Speed Limitations Fifo ModeGeneral Information Background Fifo Write60040 Read out the number of available Fifo buffers Programming Fifo ModeSoftware Buffers Theoretical maximum sample rate PCI Bus ThroughputDigital I/O 701x or 702x or pattern generator boards Fifo Mode ProgrammingBuffer processing Analog acquisition or generation boardsSpcfifowait Example Fifo generation mode== Maxbuf SpcfifostartProgramming Clock generation Internally generated sample rateStandard internal sample rate Using plain quartz with no PLL External reference clockExternal clocking Direct external clock Minimum external sample rateMaximum external samplerate in MS/s External clock with divider ExampleCHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 External TTL trigger Example for setting up the software triggerTrigger modes and appendant registers Software triggerPositive TTL trigger Example on how to set up the board for positive TTL triggerEdge triggers Trigger modes and appendant registersPositive and negative TTL trigger Trigger modes Standard ModeOption Multiple Replay Output modesTrigger modes Option Multiple Replay Resulting start delaysValue Direction Description General information and trigger delayOption Gated Replay Option Gated ReplaySpctriggermode Tmttlpos Example programAllowed trigger modes External TTL edge triggerTransfer Data Option Extra I/ODigital I/Os Channel directionAnalog Outputs Programming exampleAnalog Outputs Option Extra I/O Synchronization with option starhub Synchronization OptionDifferent synchronization options Synchronization with option cascadingWrite Data to on-board memory output boards only Setup order for the different synchronization optionsSet up the board parameters Example of board setup for three boardsDefine the remaining boards as trigger slaves Define the boards for trigger masterExample of board #2 set as trigger master 3a Define synchronization or triggerArm the boards for synchronization Define the board for clock masterExample board number 0 is clock master Define the remaining boards as clock slavesExample for data reading Start all of the trigger master boardsWait for the end of the measurement Read data from the on-board memory acquisition boards onlySpcsyncslavefifo Allocate the Fifo software buffers2a Write first data for output boards SpcsyncmasterfifoAs trigger slaves 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx Additions for synchronizing different boardsGeneral information Calculating the clock dividersBoard type 3025 3131 Setting up the clock dividerBoard type 3122 3120 40 MS/sAdditions for equal boards with different sample rates Resulting delays using different boards or speedsDelay in standard non Fifo modes Delay in Fifo modeAppendix Error CodesError name Value hex Value dec Error description AppendixPin assignment of the multipin connector Extra I/O with external connectorOption -XMFPin assignment of the multipin cable D15 D13 D11 Pin assignment of the internal multipin connectorExtra I/O with internal connector Option -XIO D14 D12 D10
Top Page Image Contents