Spectrum Brands MI.61XX manual Synchronization Option, Different synchronization options

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Synchronization (Option)

The different synchronization options

 

 

Synchronization (Option)

This option allows the connection of multiple boards to generate a multi-channel system. It is possible to synchronize multiple Spectrum boards of the same type as well as different board types. Therefore the synchronized boards must be linked concerning the board’s system clock and the trigger signals.

If no synchronization is desired for a certain board you can exclude it by setting the register shown in the following table. This must be done seperately for every board that should not work synchronized.

Register

Value

Direction

Description

SPC_COMMAND

0

r/w

Command register of the board

 

SPC_NOSYNC

120

Disables the synchronization globally.

The different synchronization options

Synchronization with option cascading

With the option cascading up to four Spectrum boards can be synchronized. All boards are connected with one synchronization cable on their sync-connectors (for details please refer to the chapter about installing the hardware).

As the synchronization lines are organized as a bus topology, there is a need for termination at both ends of the bus. This is done in factory for the both end-boards. The maximum possible two middle-boards have no termination on board.

When synchronizing multiple boards, one is set to be the clock master for all the connected boards. All the other boards are working as clock slaves. It’s also possible to temporarily disable boards from the synchronization.

The same board or another one of the connected boards can be defined as a trigger master for all boards. All trigger modes of the trigger master board can be used. It is also possible to synchronize the connected boards only for the samplerate and not for trigger. This can be useful if one generator board is continuously generating a test-

pattern, while the connected acquisition board is triggering for test results or error conditions of the device under test.

For the fact that the termination is set in factory the order of the syncronized boards cannot be changed by the user. Please refer to the boards type plate for details on the board’s termination. End boards are marked with the option „cs-end“ while middle boards are marked with the option „cs-mid“

When the boards are synchronized by the option cascading there will be a delay of about 500 ps between two adjacent boards.

The figure on the right shows the clocks of three cascaded boards with two channels each, where one end-board is de- fined as a clock master. Slave 1 is therefore a middle-board and Slave 2 is the other end-board. The resulting delay bet- ween data of the two end-boards is therefore about 1 ns.

Please keep in mind that the delay between the channels of two boards is depending on which board is actually set up as the clock master and what boards are directly adjacent to the master.

Synchronization with option starhub

With the option starhub up to 16 Spectrum boards can be synchronized. All boards are connected with a seperate synchronization cable from their sync-connectors to the starhub module, which is a piggy-back module on one Spectrum board (for details please refer to the chapter about installing the hardware).

When synchronizing multiple boards, one is set to be the clock master for all the connected boards. All the other boards are working as clock slaves. It’s also possible to temporarily disable the synchronization of one board. This board then runs individually while the other boards still are synchronized.

The same board or another one of the connected boards can be defined as a trigger master for all boards. All trigger modes of the board defined as the trigger master can be used. It is also possible to synchronize the connected boards only for the samplerate and not for trigger. This can be useful, if one generator board is continuously generating a testpattern, while the connected acquisition board is triggering for test results or error conditions of the device under test.

Additionally you can even define more than one board as a trigger master. The trigger events of all boards are combined by a logical OR, so that the first board that detects a trigger will start the boards. This OR connection is available starting with starhub hardware version V4.

(c) Spectrum GmbH

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Contents English version October 5 MI.61xxPage Software Hardware InstallationSoftware Driver Installation IntroductionStandard generation modes Fifo ModeProgramming the Board Analog OutputsAppendix Option Gated ReplayOption Extra I/O Synchronization OptionPreface IntroductionPreface General InformationMI.6110 MI.6111 Different models of the MI.61xx seriesIntroduction Extra I/O Option -XMF Additional optionsExtra I/O Option -XIO Introduction Additional options StarhubSpectrum type plate Hardware information Block diagram Technical DataFilter Dynamic ParametersOrder information Hardware informationIntroductionInstalling the board in the system Hardware InstallationSystem Requirements Installing a board with extra I/O Option -XMF Installing a board with digital inputs/outputsOnly use the included flat ribbon cables Installing multiple boards synchronized by starhubMounting the wired boards Hooking up the boardsInstalling multiple synchronized boards Software Driver Installation Software Driver InstallationInterrupt Sharing Windows InstallationVersion control Driver Update Windows Software Driver Installation Windows Windows XP Windows XP Adding boards to the Windows NT driver Windows NTOverview LinuxAutomatic load of the driver Installing the deviceNow it is possible to access the board using this device Driver infoSoftware SoftwareSoftware Overview First Test with SBenchLinux Gnu C ++ Driver InterfaceHeader files Microsoft Visual C++Include Drivers Other Windows C/C++ compilersNational Instruments LabWindows/CVI Driver functionsFunction SpcGetData Function SpcSetParamFunction SpcSetParam Function SpcSetData WindowsSpectrum GmbH Examples Delphi Pascal Programming InterfaceType definition Include DriverDelphi Pascal Programming Interface Visual Basic Examples Visual Basic Programming InterfaceVBA for Excel Examples Visual Basic Programming Interface Register tables Error handlingProgramming the Board OverviewPCI Register Example for error checkingInitialization Starting the automatic initialization routineSerial number Installed memoryHardware version Date of productionDriver version Installed features and optionsUsed interrupt line Used type of driverSpcpciserialno Powerdown and resetExample program for the board initialization SpcpcimemsizeDisabling the outputs Analog OutputsChannel Selection Important note on channels selectionRegister Value Direction Description Amplitude range Setting up the outputsOutput Amplifiers Output offsetMaximum Output Range Filter SpecificationsOutput Filters General description Standard generation modesProgramming Minimum and stepsize of memsize and posttrigger in samples Standard generation modes ProgrammingMaximum memsize Maximum posttrigger in MSamplesProgrammingStandard generation modes Starting without interrupt classic modeStarting with interrupt driven mode Command registerValue ’len’ as a 32 bit integer value Data organizationWriting data with SpcSetData Value ’start’ as a 32 bit integer valueBit Standard Mode Standard modeSample format Speed Limitations Fifo ModeGeneral Information Background Fifo Write60040 Read out the number of available Fifo buffers Programming Fifo ModeSoftware Buffers Theoretical maximum sample rate PCI Bus ThroughputDigital I/O 701x or 702x or pattern generator boards Fifo Mode ProgrammingBuffer processing Analog acquisition or generation boardsSpcfifowait Example Fifo generation mode== Maxbuf SpcfifostartProgramming Internally generated sample rate Clock generationStandard internal sample rate External reference clock Using plain quartz with no PLLExternal clocking Minimum external sample rate Direct external clockMaximum external samplerate in MS/s Example External clock with dividerCHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 External TTL trigger Example for setting up the software triggerTrigger modes and appendant registers Software triggerPositive TTL trigger Example on how to set up the board for positive TTL triggerEdge triggers Trigger modes and appendant registersPositive and negative TTL trigger Trigger modes Standard ModeOption Multiple Replay Output modesTrigger modes Option Multiple Replay Resulting start delaysValue Direction Description General information and trigger delayOption Gated Replay Option Gated ReplaySpctriggermode Tmttlpos Example programAllowed trigger modes External TTL edge triggerTransfer Data Option Extra I/ODigital I/Os Channel directionProgramming example Analog OutputsAnalog Outputs Option Extra I/O Synchronization with option starhub Synchronization OptionDifferent synchronization options Synchronization with option cascadingWrite Data to on-board memory output boards only Setup order for the different synchronization optionsSet up the board parameters Example of board setup for three boardsDefine the remaining boards as trigger slaves Define the boards for trigger masterExample of board #2 set as trigger master 3a Define synchronization or triggerArm the boards for synchronization Define the board for clock masterExample board number 0 is clock master Define the remaining boards as clock slavesExample for data reading Start all of the trigger master boardsWait for the end of the measurement Read data from the on-board memory acquisition boards onlySpcsyncslavefifo Allocate the Fifo software buffers2a Write first data for output boards SpcsyncmasterfifoAs trigger slaves 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx Additions for synchronizing different boardsGeneral information Calculating the clock dividersBoard type 3025 3131 Setting up the clock dividerBoard type 3122 3120 40 MS/sAdditions for equal boards with different sample rates Resulting delays using different boards or speedsDelay in standard non Fifo modes Delay in Fifo modeAppendix Error CodesError name Value hex Value dec Error description AppendixExtra I/O with external connectorOption -XMF Pin assignment of the multipin connectorPin assignment of the multipin cable D15 D13 D11 Pin assignment of the internal multipin connectorExtra I/O with internal connector Option -XIO D14 D12 D10
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