Spectrum Brands MI.61XX manual As trigger slaves

Page 73

Synchronization (Option)

The setup order for the different synchronization options

 

 

(8) Start all of the trigger slave boards

After having armed the synchronized boards, you must start all of the boards, that are defined as trigger slaves first. This is done with the FIFOSTART command.

Register

Value

Direction

Description

SPC_COMMAND

0

r/w

Command register of the board

 

SPC_FIFOSTART

10

Starts the board with the current register settings in FIFO mode and waits for the first interrupt.

Remember that the FIFO mode is allways interrupt driven. As a result the FIFOSTART function will not return until the first software buffer is transferred. For that reason it is absolutely necessary to start different threads for each board that runs synchronuously in FIFO mode. If this is not done a deadlock will occur and the pro- gram will not start properly.

(9) Start all of the trigger master boards

After having armed the synchronized boards, you must start all of the boards, that are defined as trigger masters.

Register

Value

Direction

Description

SPC_COMMAND

0

r/w

Command register of the board

 

SPC_FIFOSTART

10

Starts the board with the current register settings in FIFO mode and waits for the first interrupt.

This example shows how to set up three boards for synchronization in FIFO mode. Board 0 is clock master and board 2 is trigger master.

// (3) -----

trigger synchronization of trigger master board(s)

----- // board 2 set as trigger master

SpcSetParam (hDrv[2], SPC_COMMAND,

SPC_SYNCTRIGGERMASTER);

// (4) -----

trigger synchronization of trigger slave boards

-----

SpcSetParam (hDrv[0], SPC_COMMAND,

SPC_SYNCTRIGGERSLAVE);

// as trigger slaves

SpcSetParam (hDrv[1], SPC_COMMAND,

SPC_SYNCTRIGGERSLAVE);

// as trigger slaves

// (5) -----

synchronization information for clock master board

-----

SpcSetParam (hDrv[0], SPC_COMMAND,

SPC_SYNCMASTERFIFO);

 

// (6) -----

synchronization information for clock slave boards

-----

SpcSetParam (hDrv[1], SPC_COMMAND,

SPC_SYNCSLAVEFIFO);

 

SpcSetParam (hDrv[2], SPC_COMMAND,

SPC_SYNCSLAVEFIFO);

 

// (7) -----

start the synchronization -----

 

SpcSetParam (hDrv[0], SPC_COMMAND,

SPC_SYNCSTART);

 

// (8) -----

start the FIFO tasks. Trigger slaves are started first -----

CreateThread

(NULL, 0, &dwFIFOTask, (void*) hDrv[0], 0, &dwThreadId[b]);

CreateThread

(NULL, 0, &dwFIFOTask, (void*) hDRV[1], 0, &dwThreadId[b]);

// (9) -----

start the trigger master FIFO task -----

 

CreateThread

(NULL, 0, &dwFIFOTask, (void*) hDrv[2], 0, &dwThreadId[hDrv[2]]);

 

 

 

 

It is assumed, that the created threads start in the same order as they are called from within the program. As described before, starting of the FIFO mode in synchronization has to be done in different threads to avoid a deadlock. A simple example for a FIFO thread can be found below.

Example of FIFO task. It simply starts the boards and counts the buffers that have been transfered:

unsigned long __stdcall dwFIFOTask (void* phDrv)

 

{

hDrv = (int16) phDrv;

 

int16

 

int32

lCmd = SPC_FIFOSTART;

 

int16

nBufIdx = 0, nErr;

 

int32

lTotalBuf;

 

 

lTotalBuf = 0;

 

 

do

 

 

 

{

 

 

// wait for buffer

nErr = SpcSetParam (hDrv, SPC_COMMAND, lCmd);

lCmd = SPC_FIFOWAIT;

 

// here you can do

printf ("Board %d

Buffer %d total buffers: %d\n", nIdx, nBufIdx, lTotalBuf);// e.g. calculations

SpcSetParam (hDrv, SPC_COMMAND, SPC_FIFO_BUFREADY0 + nBufIdx);

// just a printf here

// release buffer

nBufIdx++;

lTotalBuf++;

if (nBufIdx == FIFO_BUFFERS) nBufIdx = 0;

}

while (nErr == ERR_OK);

return 0;

}

(c) Spectrum GmbH

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Contents English version October 5 MI.61xxPage Software Driver Installation Hardware InstallationIntroduction SoftwareProgramming the Board Fifo ModeAnalog Outputs Standard generation modesOption Extra I/O Option Gated ReplaySynchronization Option AppendixPreface IntroductionGeneral Information PrefaceMI.6110 MI.6111 Different models of the MI.61xx seriesIntroduction Extra I/O Option -XMF Additional optionsExtra I/O Option -XIO Introduction Additional options StarhubSpectrum type plate Hardware information Block diagram Technical DataOrder information Dynamic ParametersHardware informationIntroduction FilterInstalling the board in the system Hardware InstallationSystem Requirements Installing a board with extra I/O Option -XMF Installing a board with digital inputs/outputsMounting the wired boards Installing multiple boards synchronized by starhubHooking up the boards Only use the included flat ribbon cablesInstalling multiple synchronized boards Software Driver Installation Software Driver InstallationInterrupt Sharing Windows InstallationVersion control Driver Update Windows Software Driver Installation Windows Windows XP Windows XP Adding boards to the Windows NT driver Windows NTOverview LinuxNow it is possible to access the board using this device Installing the deviceDriver info Automatic load of the driverSoftware Overview SoftwareFirst Test with SBench SoftwareHeader files ++ Driver InterfaceMicrosoft Visual C++ Linux Gnu CNational Instruments LabWindows/CVI Other Windows C/C++ compilersDriver functions Include DriversFunction SpcSetParam Function SpcSetParamFunction SpcSetData Windows Function SpcGetDataSpectrum GmbH Type definition Delphi Pascal Programming InterfaceInclude Driver ExamplesDelphi Pascal Programming Interface Visual Basic Examples Visual Basic Programming InterfaceVBA for Excel Examples Visual Basic Programming Interface Programming the Board Error handlingOverview Register tablesInitialization Example for error checkingStarting the automatic initialization routine PCI RegisterHardware version Installed memoryDate of production Serial numberUsed interrupt line Installed features and optionsUsed type of driver Driver versionExample program for the board initialization Powerdown and resetSpcpcimemsize SpcpciserialnoChannel Selection Analog OutputsImportant note on channels selection Disabling the outputsOutput Amplifiers Setting up the outputsOutput offset Register Value Direction Description Amplitude rangeMaximum Output Range Filter SpecificationsOutput Filters General description Standard generation modesProgramming Maximum memsize Standard generation modes ProgrammingMaximum posttrigger in MSamples Minimum and stepsize of memsize and posttrigger in samplesStarting with interrupt driven mode Starting without interrupt classic modeCommand register ProgrammingStandard generation modesWriting data with SpcSetData Data organizationValue ’start’ as a 32 bit integer value Value ’len’ as a 32 bit integer valueBit Standard Mode Standard modeSample format General Information Fifo ModeBackground Fifo Write Speed LimitationsSoftware Buffers Programming Fifo ModeTheoretical maximum sample rate PCI Bus Throughput 60040 Read out the number of available Fifo buffersBuffer processing Fifo Mode ProgrammingAnalog acquisition or generation boards Digital I/O 701x or 702x or pattern generator boards== Maxbuf Example Fifo generation modeSpcfifostart SpcfifowaitProgramming Internally generated sample rate Clock generationStandard internal sample rate External reference clock Using plain quartz with no PLLExternal clocking Minimum external sample rate Direct external clockMaximum external samplerate in MS/s Example External clock with dividerCHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 Trigger modes and appendant registers Example for setting up the software triggerSoftware trigger External TTL triggerEdge triggers Example on how to set up the board for positive TTL triggerTrigger modes and appendant registers Positive TTL triggerPositive and negative TTL trigger Option Multiple Replay Standard ModeOutput modes Trigger modesTrigger modes Option Multiple Replay Resulting start delaysOption Gated Replay General information and trigger delayOption Gated Replay Value Direction DescriptionAllowed trigger modes Example programExternal TTL edge trigger Spctriggermode TmttlposDigital I/Os Option Extra I/OChannel direction Transfer DataProgramming example Analog OutputsAnalog Outputs Option Extra I/O Different synchronization options Synchronization OptionSynchronization with option cascading Synchronization with option starhubSet up the board parameters Setup order for the different synchronization optionsExample of board setup for three boards Write Data to on-board memory output boards onlyExample of board #2 set as trigger master Define the boards for trigger master3a Define synchronization or trigger Define the remaining boards as trigger slavesExample board number 0 is clock master Define the board for clock masterDefine the remaining boards as clock slaves Arm the boards for synchronizationWait for the end of the measurement Start all of the trigger master boardsRead data from the on-board memory acquisition boards only Example for data reading2a Write first data for output boards Allocate the Fifo software buffersSpcsyncmasterfifo SpcsyncslavefifoAs trigger slaves General information Additions for synchronizing different boardsCalculating the clock dividers 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xxBoard type 3122 3120 Setting up the clock divider40 MS/s Board type 3025 3131Delay in standard non Fifo modes Resulting delays using different boards or speedsDelay in Fifo mode Additions for equal boards with different sample ratesError name Value hex Value dec Error description Error CodesAppendix AppendixExtra I/O with external connectorOption -XMF Pin assignment of the multipin connectorPin assignment of the multipin cable Extra I/O with internal connector Option -XIO Pin assignment of the internal multipin connectorD14 D12 D10 D15 D13 D11
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