Spectrum Brands MI.61XX manual Clock generation, Internally generated sample rate

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Overview

Clock generation

 

 

Clock generation

Overview

The Spectrum boards offer a wide variety of different clock modes to match all the customers needs. All the clock modes are described in detail with programming examples below. This chapter simply gives you an overview which clock mode to select:

Standard internal sample rate

PLL with internal 40 MHz reference. This is the easiest way to generate a sample rate with no need for additional external clock signals. The sample rate has a fine resolution.

Quartz and divider

Internal quarz clock with divider. For applications that need a lower clock jitter than the PLL produces. The possible sample rates are restricted to the values of the divider.

External reference clock

PLL with external 1 MHz to 125 MHz reference clock. This provides a very good clock accuracy if a stable external reference clock is used.It also allows the easy synchronization with an external source.

External clock

Any clock can be fed in that matches the specification of the board. The external clock signal can be used to synchronize the board on a system clock or to feed in an exact matching sample rate.

External clock with divider

The externally fed in clock can be divided to generate a low-jitter sample rate of a slower speed than the external clock available.

There is a more detailed description of the clock generation part available as an application note. There some more background information and details of the internal structure are explained.

Internally generated sample rate

Standard internal sample rate

The internal sample rate is generated in default mode by a PLL and dividers out of an internal 40 MHz frequency reference. In most cases the user does not need to care on how the desired sample rate is generated by multiplying and dividing internally. You simply write the desired sample rate to the according register shown in the table below. If you want to make sure the sample rate has been set correctly you can also read out the register and the driver will give you back the sample rate that is matching your desired one best.

Register

Value

Direction

Description

SPC_SAMPLERATE

20000

w

Defines the sample rate in Hz for internal sample rate generation.

 

 

r

Read out the internal sample rate that is nearest matching to the desired one.

If a sample rate is generated internally, you can additionally enable the clock output. The clock will be available on the external clock con- nector and can be used to synchronize external equipment with the board.

Register

Value

 

Direction

 

Description

SPC_EXTERNOUT

20110

 

r/w

 

Enables the clock output on the external clock connector. Only possible with internal clocking.

Example on writing and reading internal sample rate

 

 

 

 

 

 

 

SpcSetParam (hDrv, SPC_SAMPLERATE,

1000000);

 

// Set internal sample rate to 1 MHz

SpcSetParam (hDrv, SPC_EXTERNOUT,

1);

 

// enable the clock output of that 1 MHz

SpcGetParam (hDrv, SPC_SAMPLERATE,

&lSamplerate);

// Read back the sample rate that has been programmed

printf („Samplerate = %d\n“, lSamplerate);

// print it. Output should be „Samplerate = 1000000“

Minimum internal sample rate

The minimum internal sample rate is limited on all boards to 1 kHz and the maximum sample rate depends on the specific type of board. The maximum sample rates for your type of board are shown in the tables below.

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MI.61xx Manual

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Page 53 Page 55
Contents MI.61xx English version October 5Page Introduction Hardware InstallationSoftware Driver Installation SoftwareAnalog Outputs Fifo ModeProgramming the Board Standard generation modesSynchronization Option Option Gated ReplayOption Extra I/O AppendixGeneral Information IntroductionPreface PrefaceDifferent models of the MI.61xx series MI.6110 MI.6111Introduction Additional options Extra I/O Option -XMFExtra I/O Option -XIO Starhub Introduction Additional optionsSpectrum type plate Block diagram Technical Data Hardware informationHardware informationIntroduction Dynamic ParametersOrder information FilterHardware Installation Installing the board in the systemSystem Requirements Installing a board with digital inputs/outputs Installing a board with extra I/O Option -XMFHooking up the boards Installing multiple boards synchronized by starhubMounting the wired boards Only use the included flat ribbon cablesInstalling multiple synchronized boards Software Driver Installation Software Driver InstallationInterrupt Sharing Installation WindowsVersion control Driver Update Windows Software Driver Installation Windows Windows XP Windows XP Windows NT Adding boards to the Windows NT driverLinux OverviewDriver info Installing the deviceNow it is possible to access the board using this device Automatic load of the driverFirst Test with SBench SoftwareSoftware Overview SoftwareMicrosoft Visual C++ ++ Driver InterfaceHeader files Linux Gnu CDriver functions Other Windows C/C++ compilersNational Instruments LabWindows/CVI Include DriversFunction SpcSetData Windows Function SpcSetParamFunction SpcSetParam Function SpcGetDataSpectrum GmbH Include Driver Delphi Pascal Programming InterfaceType definition ExamplesDelphi Pascal Programming Interface Visual Basic Programming Interface Visual Basic ExamplesVBA for Excel Examples Visual Basic Programming Interface Overview Error handlingProgramming the Board Register tablesStarting the automatic initialization routine Example for error checkingInitialization PCI RegisterDate of production Installed memoryHardware version Serial numberUsed type of driver Installed features and optionsUsed interrupt line Driver versionSpcpcimemsize Powerdown and resetExample program for the board initialization SpcpciserialnoImportant note on channels selection Analog OutputsChannel Selection Disabling the outputsOutput offset Setting up the outputsOutput Amplifiers Register Value Direction Description Amplitude rangeFilter Specifications Maximum Output RangeOutput Filters Standard generation modes General descriptionProgramming Maximum posttrigger in MSamples Standard generation modes ProgrammingMaximum memsize Minimum and stepsize of memsize and posttrigger in samplesCommand register Starting without interrupt classic modeStarting with interrupt driven mode ProgrammingStandard generation modesValue ’start’ as a 32 bit integer value Data organizationWriting data with SpcSetData Value ’len’ as a 32 bit integer valueStandard mode Bit Standard ModeSample format Background Fifo Write Fifo ModeGeneral Information Speed LimitationsTheoretical maximum sample rate PCI Bus Throughput Programming Fifo ModeSoftware Buffers 60040 Read out the number of available Fifo buffersAnalog acquisition or generation boards Fifo Mode ProgrammingBuffer processing Digital I/O 701x or 702x or pattern generator boardsSpcfifostart Example Fifo generation mode== Maxbuf SpcfifowaitProgramming Clock generation Internally generated sample rateStandard internal sample rate Using plain quartz with no PLL External reference clockExternal clocking Direct external clock Minimum external sample rateMaximum external samplerate in MS/s External clock with divider ExampleCHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 Software trigger Example for setting up the software triggerTrigger modes and appendant registers External TTL triggerTrigger modes and appendant registers Example on how to set up the board for positive TTL triggerEdge triggers Positive TTL triggerPositive and negative TTL trigger Output modes Standard ModeOption Multiple Replay Trigger modesResulting start delays Trigger modes Option Multiple ReplayOption Gated Replay General information and trigger delayOption Gated Replay Value Direction DescriptionExternal TTL edge trigger Example programAllowed trigger modes Spctriggermode TmttlposChannel direction Option Extra I/ODigital I/Os Transfer DataAnalog Outputs Programming exampleAnalog Outputs Option Extra I/O Synchronization with option cascading Synchronization OptionDifferent synchronization options Synchronization with option starhubExample of board setup for three boards Setup order for the different synchronization optionsSet up the board parameters Write Data to on-board memory output boards only3a Define synchronization or trigger Define the boards for trigger masterExample of board #2 set as trigger master Define the remaining boards as trigger slavesDefine the remaining boards as clock slaves Define the board for clock masterExample board number 0 is clock master Arm the boards for synchronizationRead data from the on-board memory acquisition boards only Start all of the trigger master boardsWait for the end of the measurement Example for data readingSpcsyncmasterfifo Allocate the Fifo software buffers2a Write first data for output boards SpcsyncslavefifoAs trigger slaves Calculating the clock dividers Additions for synchronizing different boardsGeneral information 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx40 MS/s Setting up the clock dividerBoard type 3122 3120 Board type 3025 3131Delay in Fifo mode Resulting delays using different boards or speedsDelay in standard non Fifo modes Additions for equal boards with different sample ratesAppendix Error CodesError name Value hex Value dec Error description AppendixPin assignment of the multipin connector Extra I/O with external connectorOption -XMFPin assignment of the multipin cable D14 D12 D10 Pin assignment of the internal multipin connectorExtra I/O with internal connector Option -XIO D15 D13 D11
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