Spectrum Brands MI.61XX manual Setting up the clock divider, Board type 3122 3120, 40 MS/s

Page 75

Synchronization (Option)	The setup order for the different synchronization options

Setting up the clock divider

The clock divider can easily be set by the following register. Please keep in mind that the divider must be set for every synchronized board to have synchronization working correctly. For more details on the board’s clocking modes please refer to the according chapter in this ma- nual.

Register	Value	Direction	Description
SPC_CLOCKDIV	20040	r/w	Extra clock divider for synchronizing different boards.

Available divider values

1	2	4	8	10	16	20	40	50	80	100	200
400	500	800	1000	2000

Although this setup is looking very complicated at first glance, it is not really difficult to set up different boards to work synchronously with the same speed. To give you an idea on how to setup the boards the calculations are shown in the following two examples.

Each example contains of a simple setup of two synchronized boards. It is assumed that all of the available channels on the dedicated boards have been activated.

Example calculation with synchronous speed where slave clock is divided

Board type	3122	3120
Channels available	8 x 12 bit A/D	2 x 12 bit A/D
Desired sample rate	10 MS/s	10 MS/s
Enabled channels per module	4	2
Sum sample rate	40 MS/s	20 MS/s
	Therefore this board is set up
	to be the clockmaster.
Sync speed	40 MS/s	40 MS/s
Clock divider	1	2
Divided sum clock	40 MS/s	20 MS/s
Enabled channels per module	4	2
Conversion speed	10 MS/s	10 MS/s

Example calculation with synchronous speed where master clock is divided

Board type	3025	3131
Channels available	2 x 12 bit A/D	4 x 12 bit A/D
Desired sample rate	20 MS/s	20 MS/s
Enabled channels per module	1	2
Sum sample rate	20 MS/s	40 MS/s
		Therefore this board is set up
		to be the clockmaster.
Sync speed	40 MS/s	40 MS/s
Clock divider	2	1
Divided sum clock	20 MS/s	40 MS/s
Enabled channels per module	1	2
Conversion speed	20 MS/s	20 MS/s

(c) Spectrum GmbH

75

Image 75

Contents English version October 5 MI.61xxPage Software Hardware InstallationSoftware Driver Installation IntroductionStandard generation modes Fifo ModeProgramming the Board Analog OutputsAppendix Option Gated ReplayOption Extra I/O Synchronization OptionPreface IntroductionPreface General InformationDifferent models of the MI.61xx series MI.6110 MI.6111Introduction Additional options Extra I/O Option -XMFExtra I/O Option -XIO Introduction Additional options StarhubSpectrum type plate Hardware information Block diagram Technical DataFilter Dynamic ParametersOrder information Hardware informationIntroductionHardware Installation Installing the board in the systemSystem Requirements Installing a board with extra I/O Option -XMF Installing a board with digital inputs/outputsOnly use the included flat ribbon cables Installing multiple boards synchronized by starhubMounting the wired boards Hooking up the boardsInstalling multiple synchronized boards Software Driver Installation Software Driver InstallationInterrupt Sharing Installation WindowsVersion control Driver Update Windows Software Driver Installation Windows Windows XP Windows XP Adding boards to the Windows NT driver Windows NTOverview LinuxAutomatic load of the driver Installing the deviceNow it is possible to access the board using this device Driver infoSoftware SoftwareSoftware Overview First Test with SBenchLinux Gnu C ++ Driver InterfaceHeader files Microsoft Visual C++Include Drivers Other Windows C/C++ compilersNational Instruments LabWindows/CVI Driver functionsFunction SpcGetData Function SpcSetParamFunction SpcSetParam Function SpcSetData WindowsSpectrum GmbH Examples Delphi Pascal Programming InterfaceType definition Include DriverDelphi Pascal Programming Interface Visual Basic Programming Interface Visual Basic ExamplesVBA for Excel Examples Visual Basic Programming Interface Register tables Error handlingProgramming the Board OverviewPCI Register Example for error checkingInitialization Starting the automatic initialization routineSerial number Installed memoryHardware version Date of productionDriver version Installed features and optionsUsed interrupt line Used type of driverSpcpciserialno Powerdown and resetExample program for the board initialization SpcpcimemsizeDisabling the outputs Analog OutputsChannel Selection Important note on channels selectionRegister Value Direction Description Amplitude range Setting up the outputsOutput Amplifiers Output offsetFilter Specifications Maximum Output RangeOutput Filters Standard generation modes General descriptionProgramming Minimum and stepsize of memsize and posttrigger in samples Standard generation modes ProgrammingMaximum memsize Maximum posttrigger in MSamplesProgrammingStandard generation modes Starting without interrupt classic modeStarting with interrupt driven mode Command registerValue ’len’ as a 32 bit integer value Data organizationWriting data with SpcSetData Value ’start’ as a 32 bit integer valueStandard mode Bit Standard ModeSample format Speed Limitations Fifo ModeGeneral Information Background Fifo Write60040 Read out the number of available Fifo buffers Programming Fifo ModeSoftware Buffers Theoretical maximum sample rate PCI Bus ThroughputDigital I/O 701x or 702x or pattern generator boards Fifo Mode ProgrammingBuffer processing Analog acquisition or generation boardsSpcfifowait Example Fifo generation mode== Maxbuf SpcfifostartProgramming Clock generation Internally generated sample rateStandard internal sample rate Using plain quartz with no PLL External reference clockExternal clocking Direct external clock Minimum external sample rateMaximum external samplerate in MS/s External clock with divider ExampleCHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 External TTL trigger Example for setting up the software triggerTrigger modes and appendant registers Software triggerPositive TTL trigger Example on how to set up the board for positive TTL triggerEdge triggers Trigger modes and appendant registersPositive and negative TTL trigger Trigger modes Standard ModeOption Multiple Replay Output modesTrigger modes Option Multiple Replay Resulting start delaysValue Direction Description General information and trigger delayOption Gated Replay Option Gated ReplaySpctriggermode Tmttlpos Example programAllowed trigger modes External TTL edge triggerTransfer Data Option Extra I/ODigital I/Os Channel directionAnalog Outputs Programming exampleAnalog Outputs Option Extra I/O Synchronization with option starhub Synchronization OptionDifferent synchronization options Synchronization with option cascadingWrite Data to on-board memory output boards only Setup order for the different synchronization optionsSet up the board parameters Example of board setup for three boardsDefine the remaining boards as trigger slaves Define the boards for trigger masterExample of board #2 set as trigger master 3a Define synchronization or triggerArm the boards for synchronization Define the board for clock masterExample board number 0 is clock master Define the remaining boards as clock slavesExample for data reading Start all of the trigger master boardsWait for the end of the measurement Read data from the on-board memory acquisition boards onlySpcsyncslavefifo Allocate the Fifo software buffers2a Write first data for output boards SpcsyncmasterfifoAs trigger slaves 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx Additions for synchronizing different boardsGeneral information Calculating the clock dividersBoard type 3025 3131 Setting up the clock dividerBoard type 3122 3120 40 MS/sAdditions for equal boards with different sample rates Resulting delays using different boards or speedsDelay in standard non Fifo modes Delay in Fifo modeAppendix Error CodesError name Value hex Value dec Error description AppendixPin assignment of the multipin connector Extra I/O with external connectorOption -XMFPin assignment of the multipin cable D15 D13 D11 Pin assignment of the internal multipin connectorExtra I/O with internal connector Option -XIO D14 D12 D10