Spectrum Brands MI.61XX Analog Outputs, Channel Selection, Important note on channels selection

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Analog Outputs

Channel Selection

 

 

Analog Outputs

Channel Selection

One key setting that influences all other possible settings is the channel enable register. An unique feature of the Spectrum boards is the possibility to program the number of channels you want to use. All on-board memory can then be used by these activated channels.

This description shows you the channel enable register for the complete board family. However your specific board may have less channels depending on the board type you purchased and did not allow you to set the maximum number of channels shown here.

Register

Value

Direction

Description

SPC_CHENABLE

11000

r/w

Sets the channel enable information for the next board run.

 

CHANNEL0

1

Activates channel 0

 

 

 

 

 

CHANNEL1

2

Activates channel 1

 

CHANNEL2

4

Activates channel 2

 

 

 

 

 

CHANNEL3

8

Activates channel 3

The channel enable register is set as a bitmap. That means one bit of the value corresponds to one channel to be activated. To activate more than one channel the values have to be combined by a bitwise OR.

Example showing how to activate 4 channels:

SpcSetParam (hDrv, SPC_CHENABLE, CHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3);

The following table shows all allowed settings for the channel enable register.

 

Channels to activate

 

 

 

 

Ch0

Ch1

Ch2

Ch3

Values to program

Value as hex

Value as decimal

X

 

 

 

CHANNEL0

1h

1

X

X

 

 

CHANNEL0 CHANNEL1

3h

3

X

 

X

 

CHANNEL0 CHANNEL2

5h

5

X

X

X

X

CHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3

Fh

15

Any channel activation mask that is not shown here is not valid. If programming another channel activation the driver automatically remaps this to the best matching activation mask. You can read out the channel en- able register to see what channel activation mask the driver has set.

Reading out the channel enable register can be done directely after setting it or later like this:

SpcGetParam (hDrv, SPC_CHENABLE, &lActivatedChannels);

printf ("Activated channels are: %ld \n", lActivatedChannels);

Important note on channels selection

As some of the manuals passages are used in more than one hardware manual most of the registers and channel settings throughout this handbook are described for the maximum number of possible channels that are available on one board of the actual series. There can be less channels on your actual type of board or bus-system. Please refer to the table above to get the actual number of available channels.

Disabling the outputs

In contrast to simply not using one or more channels by setting the channel enable registers accordingsly, the outputs can also be set to a high impedance state(tristate). Because of the internal structure the outputs can only be disabled per module by the registers shown in the table below.

Register

Value

Direction

Description

SPC_DISABLEMOD0

203000

r/w

Disables the outputs of module 0 (channel 0 and channel 1). Outputs will go to high impedance.

SPC_DISABLEMOD1

203010

r/w

Disables the outputs of module 1 (channel 2 and channel 3). Outputs will go to high impedance.

(c) Spectrum GmbH

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Contents English version October 5 MI.61xxPage Software Driver Installation Hardware InstallationIntroduction SoftwareProgramming the Board Fifo ModeAnalog Outputs Standard generation modesOption Extra I/O Option Gated ReplaySynchronization Option AppendixPreface IntroductionGeneral Information PrefaceIntroduction Different models of the MI.61xx seriesMI.6110 MI.6111 Extra I/O Option -XIO Additional optionsExtra I/O Option -XMF Introduction Additional options StarhubSpectrum type plate Hardware information Block diagram Technical DataOrder information Dynamic ParametersHardware informationIntroduction FilterSystem Requirements Hardware InstallationInstalling the board in the system Installing a board with extra I/O Option -XMF Installing a board with digital inputs/outputsMounting the wired boards Installing multiple boards synchronized by starhubHooking up the boards Only use the included flat ribbon cablesInstalling multiple synchronized boards Interrupt Sharing Software Driver InstallationSoftware Driver Installation Version control InstallationWindows Driver Update Windows Software Driver Installation Windows Windows XP Windows XP Adding boards to the Windows NT driver Windows NTOverview LinuxNow it is possible to access the board using this device Installing the deviceDriver info Automatic load of the driverSoftware Overview SoftwareFirst Test with SBench SoftwareHeader files ++ Driver InterfaceMicrosoft Visual C++ Linux Gnu CNational Instruments LabWindows/CVI Other Windows C/C++ compilersDriver functions Include DriversFunction SpcSetParam Function SpcSetParamFunction SpcSetData Windows Function SpcGetDataSpectrum GmbH Type definition Delphi Pascal Programming InterfaceInclude Driver ExamplesDelphi Pascal Programming Interface VBA for Excel Examples Visual Basic Programming InterfaceVisual Basic Examples Visual Basic Programming Interface Programming the Board Error handlingOverview Register tablesInitialization Example for error checkingStarting the automatic initialization routine PCI RegisterHardware version Installed memoryDate of production Serial numberUsed interrupt line Installed features and optionsUsed type of driver Driver versionExample program for the board initialization Powerdown and resetSpcpcimemsize SpcpciserialnoChannel Selection Analog OutputsImportant note on channels selection Disabling the outputsOutput Amplifiers Setting up the outputsOutput offset Register Value Direction Description Amplitude rangeOutput Filters Filter SpecificationsMaximum Output Range Programming Standard generation modesGeneral description Maximum memsize Standard generation modes ProgrammingMaximum posttrigger in MSamples Minimum and stepsize of memsize and posttrigger in samplesStarting with interrupt driven mode Starting without interrupt classic modeCommand register ProgrammingStandard generation modesWriting data with SpcSetData Data organizationValue ’start’ as a 32 bit integer value Value ’len’ as a 32 bit integer valueSample format Standard modeBit Standard Mode General Information Fifo ModeBackground Fifo Write Speed LimitationsSoftware Buffers Programming Fifo ModeTheoretical maximum sample rate PCI Bus Throughput 60040 Read out the number of available Fifo buffersBuffer processing Fifo Mode ProgrammingAnalog acquisition or generation boards Digital I/O 701x or 702x or pattern generator boards== Maxbuf Example Fifo generation modeSpcfifostart SpcfifowaitProgramming Standard internal sample rate Clock generationInternally generated sample rate External clocking Using plain quartz with no PLLExternal reference clock Maximum external samplerate in MS/s Direct external clockMinimum external sample rate CHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 External clock with dividerExample Trigger modes and appendant registers Example for setting up the software triggerSoftware trigger External TTL triggerEdge triggers Example on how to set up the board for positive TTL triggerTrigger modes and appendant registers Positive TTL triggerPositive and negative TTL trigger Option Multiple Replay Standard ModeOutput modes Trigger modesTrigger modes Option Multiple Replay Resulting start delaysOption Gated Replay General information and trigger delayOption Gated Replay Value Direction DescriptionAllowed trigger modes Example programExternal TTL edge trigger Spctriggermode TmttlposDigital I/Os Option Extra I/OChannel direction Transfer DataAnalog Outputs Option Extra I/O Analog OutputsProgramming example Different synchronization options Synchronization OptionSynchronization with option cascading Synchronization with option starhubSet up the board parameters Setup order for the different synchronization optionsExample of board setup for three boards Write Data to on-board memory output boards onlyExample of board #2 set as trigger master Define the boards for trigger master3a Define synchronization or trigger Define the remaining boards as trigger slavesExample board number 0 is clock master Define the board for clock masterDefine the remaining boards as clock slaves Arm the boards for synchronizationWait for the end of the measurement Start all of the trigger master boardsRead data from the on-board memory acquisition boards only Example for data reading2a Write first data for output boards Allocate the Fifo software buffersSpcsyncmasterfifo SpcsyncslavefifoAs trigger slaves General information Additions for synchronizing different boardsCalculating the clock dividers 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xxBoard type 3122 3120 Setting up the clock divider40 MS/s Board type 3025 3131Delay in standard non Fifo modes Resulting delays using different boards or speedsDelay in Fifo mode Additions for equal boards with different sample ratesError name Value hex Value dec Error description Error CodesAppendix AppendixPin assignment of the multipin cable Pin assignment of the multipin connectorExtra I/O with external connectorOption -XMF Extra I/O with internal connector Option -XIO Pin assignment of the internal multipin connectorD14 D12 D10 D15 D13 D11
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