Spectrum Brands MI.61XX manual Option Multiple Replay, Output modes, Trigger modes, Standard Mode

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Option Multiple Replay

Output modes

 

 

Option Multiple Replay

The option Multiple Replay allows the generation of data blocks with multiple trigger events without restarting the hardware. The on-board memory will be divided into several segments of the same size. Each segment will be replayed when a trigger event occures.

Output modes

Standard Mode

With every detected trigger event one data block is replayed. The length of one Multiple Replay segment is set by the value of the posttrigger register. The total amount of samples to be replayed is defined by the memsize register.

In most cases memsize will be set to a a multiple of the segment size (postcounter). The table below shows the register for enabling Multiple Replay. For detailed information on how to setup and start the standard replay mode please refer to the according chapter earlier in this manual.

Multiple Replay is not compatible with continuous output.

Register

Value

Direction

Description

SPC_MULTI

220000

r/w

Enables Multiple Replay mode.

 

 

 

 

SPC_MEMSIZE

10000

r/w

Defines the total amount of samples to be replayed.

SPC_POSTTRIGGER

10100

r/w

Defines the size of one Multiple Replay segment.

FIFO Mode

The Multiple Replay in FIFO Mode is similar to the Multiple Replay in Standard Mode. The segment size is also set by the postcounter register.

In contrast to the Standard mode you cannot programm a certain total amount of samples to be replayed. The gene- ration is running until the user stops it. The data is transfered FIFO block by FIFO block by the driver to the board. These blocks can be online generated by the user program. This mode significantly reduces the average data transfer rate

on the PCI bus. This enables you to use faster sample rates then you would be able to in FIFO mode without Multiple Replay.Usually the FIFO blocks are multiples of the Multiple Replay segments.

The advantage of Multiple Replay in FIFO mode is that you can stream data online from the host system to the board, so you can replay a huge amount of data from the hard disk. The table below shows the dedicated register for enabling Multiple Replay. For detailed information how to setup and start the board in FIFO mode please refer to the according chapter earlier in this manual.

Register

Value

Direction

Description

SPC_MULTI

220000

r/w

Enables Multiple Replay mode.

SPC_POSTTRIGGER

10100

r/w

Defines the size of one Multiple Replay segment.

Trigger modes

In Multiple Replay mode all of the board’s trigger modes are available except the software and pattern trigger. De- pending on the different trigger modes, the chosen sample rate, used channels and activated board synchronization, (see relevant chapter for details about synchronizing multi- ple boards) there are different delay times between the trig- ger event and the first replayed data (see figure).

This internal delay is necessary as the board is equipped with dynamic RAM, which needs refresh cycles to keep the data in memory when the board is not replaying.

The delay is fixed for a certain board setup. All possible delays in samples between the trigger event and the first re- played sample are listed in the table below.

The patterntrigger modes of digital I/O boards cannot be used with multiple replay.

(c) Spectrum GmbH

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Contents English version October 5 MI.61xxPage Software Driver Installation Hardware InstallationIntroduction SoftwareProgramming the Board Fifo ModeAnalog Outputs Standard generation modesOption Extra I/O Option Gated ReplaySynchronization Option AppendixPreface IntroductionGeneral Information PrefaceMI.6110 MI.6111 Different models of the MI.61xx seriesIntroduction Extra I/O Option -XMF Additional optionsExtra I/O Option -XIO Introduction Additional options StarhubSpectrum type plate Hardware information Block diagram Technical DataOrder information Dynamic ParametersHardware informationIntroduction FilterInstalling the board in the system Hardware InstallationSystem Requirements Installing a board with extra I/O Option -XMF Installing a board with digital inputs/outputsMounting the wired boards Installing multiple boards synchronized by starhubHooking up the boards Only use the included flat ribbon cablesInstalling multiple synchronized boards Software Driver Installation Software Driver InstallationInterrupt Sharing Windows InstallationVersion control Driver Update Windows Software Driver Installation Windows Windows XP Windows XP Adding boards to the Windows NT driver Windows NTOverview LinuxNow it is possible to access the board using this device Installing the deviceDriver info Automatic load of the driverSoftware Overview SoftwareFirst Test with SBench SoftwareHeader files ++ Driver InterfaceMicrosoft Visual C++ Linux Gnu CNational Instruments LabWindows/CVI Other Windows C/C++ compilersDriver functions Include DriversFunction SpcSetParam Function SpcSetParamFunction SpcSetData Windows Function SpcGetDataSpectrum GmbH Type definition Delphi Pascal Programming InterfaceInclude Driver ExamplesDelphi Pascal Programming Interface Visual Basic Examples Visual Basic Programming InterfaceVBA for Excel Examples Visual Basic Programming Interface Programming the Board Error handlingOverview Register tablesInitialization Example for error checkingStarting the automatic initialization routine PCI RegisterHardware version Installed memoryDate of production Serial numberUsed interrupt line Installed features and optionsUsed type of driver Driver versionExample program for the board initialization Powerdown and resetSpcpcimemsize SpcpciserialnoChannel Selection Analog OutputsImportant note on channels selection Disabling the outputsOutput Amplifiers Setting up the outputsOutput offset Register Value Direction Description Amplitude rangeMaximum Output Range Filter SpecificationsOutput Filters General description Standard generation modesProgramming Maximum memsize Standard generation modes ProgrammingMaximum posttrigger in MSamples Minimum and stepsize of memsize and posttrigger in samplesStarting with interrupt driven mode Starting without interrupt classic modeCommand register ProgrammingStandard generation modesWriting data with SpcSetData Data organizationValue ’start’ as a 32 bit integer value Value ’len’ as a 32 bit integer valueBit Standard Mode Standard modeSample format General Information Fifo ModeBackground Fifo Write Speed LimitationsSoftware Buffers Programming Fifo ModeTheoretical maximum sample rate PCI Bus Throughput 60040 Read out the number of available Fifo buffersBuffer processing Fifo Mode ProgrammingAnalog acquisition or generation boards Digital I/O 701x or 702x or pattern generator boards== Maxbuf Example Fifo generation modeSpcfifostart SpcfifowaitProgramming Internally generated sample rate Clock generationStandard internal sample rate External reference clock Using plain quartz with no PLLExternal clocking Minimum external sample rate Direct external clockMaximum external samplerate in MS/s Example External clock with dividerCHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 Trigger modes and appendant registers Example for setting up the software triggerSoftware trigger External TTL triggerEdge triggers Example on how to set up the board for positive TTL triggerTrigger modes and appendant registers Positive TTL triggerPositive and negative TTL trigger Option Multiple Replay Standard ModeOutput modes Trigger modesTrigger modes Option Multiple Replay Resulting start delaysOption Gated Replay General information and trigger delayOption Gated Replay Value Direction DescriptionAllowed trigger modes Example programExternal TTL edge trigger Spctriggermode TmttlposDigital I/Os Option Extra I/OChannel direction Transfer DataProgramming example Analog OutputsAnalog Outputs Option Extra I/O Different synchronization options Synchronization OptionSynchronization with option cascading Synchronization with option starhubSet up the board parameters Setup order for the different synchronization optionsExample of board setup for three boards Write Data to on-board memory output boards onlyExample of board #2 set as trigger master Define the boards for trigger master3a Define synchronization or trigger Define the remaining boards as trigger slavesExample board number 0 is clock master Define the board for clock masterDefine the remaining boards as clock slaves Arm the boards for synchronizationWait for the end of the measurement Start all of the trigger master boardsRead data from the on-board memory acquisition boards only Example for data reading2a Write first data for output boards Allocate the Fifo software buffersSpcsyncmasterfifo SpcsyncslavefifoAs trigger slaves General information Additions for synchronizing different boardsCalculating the clock dividers 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xxBoard type 3122 3120 Setting up the clock divider40 MS/s Board type 3025 3131Delay in standard non Fifo modes Resulting delays using different boards or speedsDelay in Fifo mode Additions for equal boards with different sample ratesError name Value hex Value dec Error description Error CodesAppendix AppendixExtra I/O with external connectorOption -XMF Pin assignment of the multipin connectorPin assignment of the multipin cable Extra I/O with internal connector Option -XIO Pin assignment of the internal multipin connectorD14 D12 D10 D15 D13 D11
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