Spectrum Brands MI.61XX manual Option Extra I/O, Digital I/Os, Channel direction, Transfer Data

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Option Extra I/O

Digital I/Os

 

 

Option Extra I/O

Digital I/Os

With this simple-to-use enhancement it is possible to control a wide range of external instruments or other equipment. Therefore you have several digital I/Os and the 4 analog outputs available. All extra I/O lines are completely independent from the board’s function, data di- rection or sample rate and directly controlled by software (asynchronous I/Os).

The extra I/O option is useful if an external amplifier should be controlled, any kind of signal source must be programmed, an antenna must be adjusted, a status information from external machine has to be obtained or different test signals have to be routed to the board.

It is not possible to use this option together with the star hub or timestamp option, because there is just space for one piggyback module on the on-board expansion slot.

Channel direction

Option -XMF (external connector)

The additional inputs and outputs are mounted on an extra bracket.

The direction of the 24 available digital lines can be programmed for every group of eight lines. The table below shows the direction register and the possible values. To combine the values so simply have to OR them bitwise.

Register

Value

Direction

Description

 

SPC_XIO_DIRECTION

47100

r/w

Defines bytewise the direction of the digital I/O lines. The values can be combined by a bitwise OR.

 

XD_CH0_INPUT

0

Sets the direction of channel 0 (bit D7…D0) to input.

 

 

 

 

 

XD_CH1_INPUT

0

Sets the direction of channel 1 (bit D15…D8) to input.

 

 

 

 

 

XD_CH2_INPUT

0

Sets the direction of channel 2 (bit D23…D16) to input.

 

XD_CH0_OUTPUT

1

Sets the direction of channel 0 (bit D7…D0) to output.

 

 

 

 

 

 

XD_CH1_OUTPUT

2

Sets the direction of channel 1

(bit D15…D8) to output.

 

 

 

 

 

 

XD_CH2_OUTPUT

4

Sets the direction of channel 2

(bit D23…D16) to output.

Option -XIO (internal connector)

The additional inputs and outputs are available through an internal connector directely on the extra I/O piggiback module.

The direction of the 16 available digital lines can be programmed for every group of eight lines. The table below shows the direction register and the possible values. To combine the values so simply have to OR them bitwise.

Register

Value

Direction

Description

 

SPC_XIO_DIRECTION

47100

r/w

Defines bytewise the direction of the digital I/O lines. The values can be combined by a bitwise OR.

 

XD_CH0_INPUT

0

Sets the direction of channel 0 (bit D7…D0) to input.

 

 

 

 

 

 

XD_CH1_INPUT

0

Sets the direction of channel 1

(bit D15…D8) to input.

 

XD_CH0_OUTPUT

1

Sets the direction of channel 0

(bit D7…D0) to output.

 

XD_CH1_OUTPUT

2

Sets the direction of channel 1

(bit D15…D8) to output.

Transfer Data

The outputs can be written or read by a single 32 bit register. If the register is read, the actual pin data will be taken. Therefore reading the data of outputs gives back the generated pattern. The single bits of the digital I/O lines correspond with the bitnumber of the 32 bit register. Values written to the most significant byte will be ignored.

Register

Value

Direction

Description

SPC_XIO_DIGITALIO

47110

r

Reads the data directly from the pins of all digital I/O lines either if they are declared as inputs or

 

 

 

outputs.

SPC_XIO_DIGITALIO

47110

w

Writes the data to all digital I/O lines that are declared as outputs. Bytes that are declared as inputs

 

 

 

will ignore the written data.

(c) Spectrum GmbH

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Contents English version October 5 MI.61xxPage Software Driver Installation Hardware InstallationIntroduction SoftwareProgramming the Board Fifo ModeAnalog Outputs Standard generation modesOption Extra I/O Option Gated ReplaySynchronization Option AppendixPreface IntroductionGeneral Information PrefaceIntroduction Different models of the MI.61xx seriesMI.6110 MI.6111 Extra I/O Option -XIO Additional optionsExtra I/O Option -XMF Introduction Additional options StarhubSpectrum type plate Hardware information Block diagram Technical DataOrder information Dynamic ParametersHardware informationIntroduction FilterSystem Requirements Hardware InstallationInstalling the board in the system Installing a board with extra I/O Option -XMF Installing a board with digital inputs/outputsMounting the wired boards Installing multiple boards synchronized by starhubHooking up the boards Only use the included flat ribbon cablesInstalling multiple synchronized boards Interrupt Sharing Software Driver InstallationSoftware Driver Installation Version control InstallationWindows Driver Update Windows Software Driver Installation Windows Windows XP Windows XP Adding boards to the Windows NT driver Windows NTOverview LinuxNow it is possible to access the board using this device Installing the deviceDriver info Automatic load of the driverSoftware Overview SoftwareFirst Test with SBench SoftwareHeader files ++ Driver InterfaceMicrosoft Visual C++ Linux Gnu CNational Instruments LabWindows/CVI Other Windows C/C++ compilersDriver functions Include DriversFunction SpcSetParam Function SpcSetParamFunction SpcSetData Windows Function SpcGetDataSpectrum GmbH Type definition Delphi Pascal Programming InterfaceInclude Driver ExamplesDelphi Pascal Programming Interface VBA for Excel Examples Visual Basic Programming InterfaceVisual Basic Examples Visual Basic Programming Interface Programming the Board Error handlingOverview Register tablesInitialization Example for error checkingStarting the automatic initialization routine PCI RegisterHardware version Installed memoryDate of production Serial numberUsed interrupt line Installed features and optionsUsed type of driver Driver versionExample program for the board initialization Powerdown and resetSpcpcimemsize SpcpciserialnoChannel Selection Analog OutputsImportant note on channels selection Disabling the outputsOutput Amplifiers Setting up the outputsOutput offset Register Value Direction Description Amplitude rangeOutput Filters Filter SpecificationsMaximum Output Range Programming Standard generation modesGeneral description Maximum memsize Standard generation modes ProgrammingMaximum posttrigger in MSamples Minimum and stepsize of memsize and posttrigger in samplesStarting with interrupt driven mode Starting without interrupt classic modeCommand register ProgrammingStandard generation modesWriting data with SpcSetData Data organizationValue ’start’ as a 32 bit integer value Value ’len’ as a 32 bit integer valueSample format Standard modeBit Standard Mode General Information Fifo ModeBackground Fifo Write Speed LimitationsSoftware Buffers Programming Fifo ModeTheoretical maximum sample rate PCI Bus Throughput 60040 Read out the number of available Fifo buffersBuffer processing Fifo Mode ProgrammingAnalog acquisition or generation boards Digital I/O 701x or 702x or pattern generator boards== Maxbuf Example Fifo generation modeSpcfifostart SpcfifowaitProgramming Standard internal sample rate Clock generationInternally generated sample rate External clocking Using plain quartz with no PLLExternal reference clock Maximum external samplerate in MS/s Direct external clockMinimum external sample rate CHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 External clock with dividerExample Trigger modes and appendant registers Example for setting up the software triggerSoftware trigger External TTL triggerEdge triggers Example on how to set up the board for positive TTL triggerTrigger modes and appendant registers Positive TTL triggerPositive and negative TTL trigger Option Multiple Replay Standard ModeOutput modes Trigger modesTrigger modes Option Multiple Replay Resulting start delaysOption Gated Replay General information and trigger delayOption Gated Replay Value Direction DescriptionAllowed trigger modes Example programExternal TTL edge trigger Spctriggermode TmttlposDigital I/Os Option Extra I/OChannel direction Transfer DataAnalog Outputs Option Extra I/O Analog OutputsProgramming example Different synchronization options Synchronization OptionSynchronization with option cascading Synchronization with option starhubSet up the board parameters Setup order for the different synchronization optionsExample of board setup for three boards Write Data to on-board memory output boards onlyExample of board #2 set as trigger master Define the boards for trigger master3a Define synchronization or trigger Define the remaining boards as trigger slavesExample board number 0 is clock master Define the board for clock masterDefine the remaining boards as clock slaves Arm the boards for synchronizationWait for the end of the measurement Start all of the trigger master boardsRead data from the on-board memory acquisition boards only Example for data reading2a Write first data for output boards Allocate the Fifo software buffersSpcsyncmasterfifo SpcsyncslavefifoAs trigger slaves General information Additions for synchronizing different boardsCalculating the clock dividers 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xxBoard type 3122 3120 Setting up the clock divider40 MS/s Board type 3025 3131Delay in standard non Fifo modes Resulting delays using different boards or speedsDelay in Fifo mode Additions for equal boards with different sample ratesError name Value hex Value dec Error description Error CodesAppendix AppendixPin assignment of the multipin cable Pin assignment of the multipin connectorExtra I/O with external connectorOption -XMF Extra I/O with internal connector Option -XIO Pin assignment of the internal multipin connectorD14 D12 D10 D15 D13 D11
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