Spectrum Brands MI.61XX manual Direct external clock, Minimum external sample rate

Page 56

Internally generated sample rate

Clock generation

 

 

Direct external clock

An external clock can be fed in on the external clock connector of the board. This can be any clock, that matches the specification of the board. The external clock signal can be used to synchronize the board on a system clock or to feed in an exact matching sample rate.

Register

Value

Direction

Description

SPC_EXTERNALCLOCK

20100

r/w

Enables the external clock input. If external clock input is disabled, internal clock will be used.

The maximum values for the external clock is board dependant and shown in the table below.

Termination of the clock input

If the external connector is used as an input, either for feeding in an external reference clock or for external clocking you can enable a 50 Ohm termination on the board. If the termination is disabled, the impedance is 1 Megaohm. Please make sure that your source is capable of driving that current and that it still fulfills the clock input specification as given in teh technical data section.

Register

Value

Direction

Description

SPC_CLOCK50OHM

20120

r/w

A „1“ enables the 50 Ohm termination at the external clock connector. Only possible, when using

 

 

 

the external connector as an input.

Minimum external sample rate

The minimum external sample rate is limited on all boards to 1 MHz and the maximum sample rate depends on the specific type of board. The maximum sample rates for your type of board are shown in the tables below.

Maximum external samplerate in MS/s

Remapped channels

6110

6111

ch0

ch1

ch2

ch3

 

 

 

 

 

 

x

 

 

 

125

125

x

x

 

 

125

125

x

 

x

 

n.a.

125

x

x

x

x

n.a.

125

An external sample rate above the mentioned maximum can cause damage to the board.

Ranges for external sample rate

Due to the internal structure of the board it is essential to know for the driver in which clock range the external clock is operating. The external range register must be set according to the clock that is fed in externally.

Register

Value

Direction

Description

SPC_EXTERNRANGE

20130

r/w

Defines the range of the actual fed in external clock. Use one of the below mentioned ranges

 

EXRANGE_SINGLE

2

External Range Single

 

EXRANGE_BURST_S

4

External Range Burst S

 

 

 

 

 

EXRANGE_BURST_M

8

External Range Burst M

 

EXRANGE_BURST_L

16

External Range Burst X

 

EXRANGE_BURST_XL

32

External Range Burst XL

The range must not be left by more than 5 % when the board is running. Remember that the ranges depend on the activated channels as well, so a different board setup for external clocking must always include the related clock ranges.

This table below shows the ranges that are defined by the different range registers mentioned above. The range depends on the activated channels and the mode the board is used in. Please be sure to select the correct range. Otherwise it is possible that the board will not run properly.

ch0

ch1

ch2

ch3

Mode

EXRANGE_SINGLE

EXRANGE_BURST_S

EXRANGE_BURST_M

EXRANGE_BURST_L

EXRANGE_BURST_XL

X

 

 

 

Standard/FIFO

< 10 MHz

10 MHz up to max

 

 

 

X

X

 

 

Standard/FIFO

< 5 MHz

5 MHz up to max

 

 

 

X

 

X

 

Standard/FIFO

< 10 MHz

10 MHz up to max

 

 

 

X

X

X

X

Standard only

< 5 MHz

5 MHz up to max

 

 

 

X

X

X

X

FIFO

< 2.5 MHz

2.5 MHz up to 7.5 MHz

7.5 MHz up to 17.5 MHz

17.5 MHz up to 36 MHz

> 36 MHz

How to read this table? If you have activated all four channels and are using the board in FIFO mode and your external clock is known to be around 5 MHz you have to set the EXRANGE_BURST_S for the external range.

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MI.61xx Manual

Page 55 Page 57
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Page 55 Page 57
Contents MI.61xx English version October 5Page Hardware Installation Software Driver InstallationIntroduction SoftwareFifo Mode Programming the BoardAnalog Outputs Standard generation modesOption Gated Replay Option Extra I/OSynchronization Option AppendixIntroduction PrefaceGeneral Information PrefaceIntroduction Different models of the MI.61xx seriesMI.6110 MI.6111 Extra I/O Option -XIO Additional optionsExtra I/O Option -XMF Starhub Introduction Additional optionsSpectrum type plate Block diagram Technical Data Hardware informationDynamic Parameters Order informationHardware informationIntroduction FilterSystem Requirements Hardware InstallationInstalling the board in the system Installing a board with digital inputs/outputs Installing a board with extra I/O Option -XMFInstalling multiple boards synchronized by starhub Mounting the wired boardsHooking up the boards Only use the included flat ribbon cablesInstalling multiple synchronized boards Interrupt Sharing Software Driver InstallationSoftware Driver Installation Version control InstallationWindows Driver Update Windows Software Driver Installation Windows Windows XP Windows XP Windows NT Adding boards to the Windows NT driverLinux OverviewInstalling the device Now it is possible to access the board using this deviceDriver info Automatic load of the driverSoftware Software OverviewFirst Test with SBench Software++ Driver Interface Header filesMicrosoft Visual C++ Linux Gnu COther Windows C/C++ compilers National Instruments LabWindows/CVIDriver functions Include DriversFunction SpcSetParam Function SpcSetParamFunction SpcSetData Windows Function SpcGetDataSpectrum GmbH Delphi Pascal Programming Interface Type definitionInclude Driver ExamplesDelphi Pascal Programming Interface VBA for Excel Examples Visual Basic Programming InterfaceVisual Basic Examples Visual Basic Programming Interface Error handling Programming the BoardOverview Register tablesExample for error checking InitializationStarting the automatic initialization routine PCI RegisterInstalled memory Hardware versionDate of production Serial numberInstalled features and options Used interrupt lineUsed type of driver Driver versionPowerdown and reset Example program for the board initializationSpcpcimemsize SpcpciserialnoAnalog Outputs Channel SelectionImportant note on channels selection Disabling the outputsSetting up the outputs Output AmplifiersOutput offset Register Value Direction Description Amplitude rangeOutput Filters Filter SpecificationsMaximum Output Range Programming Standard generation modesGeneral description Standard generation modes Programming Maximum memsizeMaximum posttrigger in MSamples Minimum and stepsize of memsize and posttrigger in samplesStarting without interrupt classic mode Starting with interrupt driven modeCommand register ProgrammingStandard generation modesData organization Writing data with SpcSetDataValue ’start’ as a 32 bit integer value Value ’len’ as a 32 bit integer valueSample format Standard modeBit Standard Mode Fifo Mode General InformationBackground Fifo Write Speed LimitationsProgramming Fifo Mode Software BuffersTheoretical maximum sample rate PCI Bus Throughput 60040 Read out the number of available Fifo buffersFifo Mode Programming Buffer processingAnalog acquisition or generation boards Digital I/O 701x or 702x or pattern generator boardsExample Fifo generation mode == MaxbufSpcfifostart SpcfifowaitProgramming Standard internal sample rate Clock generationInternally generated sample rate External clocking Using plain quartz with no PLLExternal reference clock Maximum external samplerate in MS/s Direct external clockMinimum external sample rate CHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 External clock with dividerExample Example for setting up the software trigger Trigger modes and appendant registersSoftware trigger External TTL triggerExample on how to set up the board for positive TTL trigger Edge triggersTrigger modes and appendant registers Positive TTL triggerPositive and negative TTL trigger Standard Mode Option Multiple ReplayOutput modes Trigger modesResulting start delays Trigger modes Option Multiple ReplayGeneral information and trigger delay Option Gated ReplayOption Gated Replay Value Direction DescriptionExample program Allowed trigger modesExternal TTL edge trigger Spctriggermode TmttlposOption Extra I/O Digital I/OsChannel direction Transfer DataAnalog Outputs Option Extra I/O Analog OutputsProgramming example Synchronization Option Different synchronization optionsSynchronization with option cascading Synchronization with option starhubSetup order for the different synchronization options Set up the board parametersExample of board setup for three boards Write Data to on-board memory output boards onlyDefine the boards for trigger master Example of board #2 set as trigger master3a Define synchronization or trigger Define the remaining boards as trigger slavesDefine the board for clock master Example board number 0 is clock masterDefine the remaining boards as clock slaves Arm the boards for synchronizationStart all of the trigger master boards Wait for the end of the measurementRead data from the on-board memory acquisition boards only Example for data readingAllocate the Fifo software buffers 2a Write first data for output boardsSpcsyncmasterfifo SpcsyncslavefifoAs trigger slaves Additions for synchronizing different boards General informationCalculating the clock dividers 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xxSetting up the clock divider Board type 3122 312040 MS/s Board type 3025 3131Resulting delays using different boards or speeds Delay in standard non Fifo modesDelay in Fifo mode Additions for equal boards with different sample ratesError Codes Error name Value hex Value dec Error descriptionAppendix AppendixPin assignment of the multipin cable Pin assignment of the multipin connectorExtra I/O with external connectorOption -XMF Pin assignment of the internal multipin connector Extra I/O with internal connector Option -XIOD14 D12 D10 D15 D13 D11
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