Spectrum Brands MI.61XX Define the board for clock master, Example board number 0 is clock master

Page 70

The setup order for the different synchronization options

Synchronization (Option)

 

 

After you have excluded one or more of the installed boards from the synchronization trigger it is possible to change the triggermodes of these boards. So only all the boards that should work synchronously must be set up for the same trigger modes to get the synchro- nization mode working correctly.

(5) Define the board for clock master

Using the synchronization option requires one board to be set up as the clock master for all the synchronized board. It is not allowed to set more than one board to clock master.

Register

Value

Direction

Description

 

SPC_COMMAND

0

r/w

Command register of the board

 

SPC_SYNCMASTER

100

Defines the according board as the clock master for operating in standard (non FIFO) mode only.

Example: board number 0 is clock master

 

 

 

 

 

 

 

 

 

SpcSetParam (hDrv[0], SPC_COMMAND,

SPC_SYNCMASTER);

// Set board 0 to clock master

 

 

 

 

 

 

(6) Define the remaining boards as clock slaves

It is necessary to set all the remaining boards to clock slaves to obtain correct internal driver settings.

Register

Value

Direction

Description

 

SPC_COMMAND

0

r/w

Command register of the board

 

SPC_SYNCSLAVE

110

Defines the according board as a clock slave for operating in standard (non FIFO) mode only.

Settings the remining boards to clock slaves. Board number 0 is clock master in the example

 

 

 

 

 

 

SpcSetParam (hDrv[1], SPC_COMMAND,

SPC_SYNCSLAVE);

// Setting all the other boards to

SpcSetParam (hDrv[2], SPC_COMMAND,

SPC_SYNCSLAVE);

// clock slave is a must !

(7) Arm the boards for synchronization

Before you can start every single one of the synchronized boards on their own you have to arm all the synchronized boards before for the use with synchronization. The synchronization has to be started on the clock master board.

Register

Value

Direction

Description

SPC_COMMAND

0

r/w

Command register of the board

 

SPC_SYNCSTART

130

Arms all boards for the use with synchronization.

Example of starting the synchronization. Board number 0 is clock master.

SpcSetParam (hDrv[0], SPC_COMMAND,

SPC_SYNCSTART);

 

 

(8) Start all of the trigger slave boards

After having armed the synchronized boards, you must start all of the boards that are defined as trigger slaves first.

Register

Value

Direction

Description

SPC_COMMAND

0

r/w

Command register of the board

 

SPC_START

10

Starts the board with the current register settings.

 

SPC_STARTANDWAIT

11

Starts the board with the current register settings in the interrupt driven mode.

For details on how to start the board in the different modes in standard mode (non FIFO) please refer to the according chapter earlier in this manual.

If using the interrupt driven mode SPC_STARTANDWAIT it is necessary to start each board in it’s own software thread. This is necessary because the function does not return until the board has stopped again. If not using different threads this will result in a program deadlock.

Example of starting trigger slave boards. Board number 2 is trigger master.

SpcSetParam

(hDrv[0],

SPC_COMMAND,

SPC_START);

SpcSetParam

(hDrv[1],

SPC_COMMAND,

SPC_START);

 

 

 

 

70

MI.61xx Manual

Page 69 Page 71
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Page 69 Page 71
Contents MI.61xx English version October 5Page Introduction Hardware InstallationSoftware Driver Installation SoftwareAnalog Outputs Fifo ModeProgramming the Board Standard generation modesSynchronization Option Option Gated ReplayOption Extra I/O AppendixGeneral Information IntroductionPreface PrefaceMI.6110 MI.6111 Different models of the MI.61xx seriesIntroduction Extra I/O Option -XMF Additional optionsExtra I/O Option -XIO Starhub Introduction Additional optionsSpectrum type plate Block diagram Technical Data Hardware informationHardware informationIntroduction Dynamic ParametersOrder information FilterInstalling the board in the system Hardware InstallationSystem Requirements Installing a board with digital inputs/outputs Installing a board with extra I/O Option -XMFHooking up the boards Installing multiple boards synchronized by starhubMounting the wired boards Only use the included flat ribbon cablesInstalling multiple synchronized boards Software Driver Installation Software Driver InstallationInterrupt Sharing Windows InstallationVersion control Driver Update Windows Software Driver Installation Windows Windows XP Windows XP Windows NT Adding boards to the Windows NT driverLinux OverviewDriver info Installing the deviceNow it is possible to access the board using this device Automatic load of the driverFirst Test with SBench SoftwareSoftware Overview SoftwareMicrosoft Visual C++ ++ Driver InterfaceHeader files Linux Gnu CDriver functions Other Windows C/C++ compilersNational Instruments LabWindows/CVI Include DriversFunction SpcSetData Windows Function SpcSetParamFunction SpcSetParam Function SpcGetDataSpectrum GmbH Include Driver Delphi Pascal Programming InterfaceType definition ExamplesDelphi Pascal Programming Interface Visual Basic Examples Visual Basic Programming InterfaceVBA for Excel Examples Visual Basic Programming Interface Overview Error handlingProgramming the Board Register tablesStarting the automatic initialization routine Example for error checkingInitialization PCI RegisterDate of production Installed memoryHardware version Serial numberUsed type of driver Installed features and optionsUsed interrupt line Driver versionSpcpcimemsize Powerdown and resetExample program for the board initialization SpcpciserialnoImportant note on channels selection Analog OutputsChannel Selection Disabling the outputsOutput offset Setting up the outputsOutput Amplifiers Register Value Direction Description Amplitude rangeMaximum Output Range Filter SpecificationsOutput Filters General description Standard generation modesProgramming Maximum posttrigger in MSamples Standard generation modes ProgrammingMaximum memsize Minimum and stepsize of memsize and posttrigger in samplesCommand register Starting without interrupt classic modeStarting with interrupt driven mode ProgrammingStandard generation modesValue ’start’ as a 32 bit integer value Data organizationWriting data with SpcSetData Value ’len’ as a 32 bit integer valueBit Standard Mode Standard modeSample format Background Fifo Write Fifo ModeGeneral Information Speed LimitationsTheoretical maximum sample rate PCI Bus Throughput Programming Fifo ModeSoftware Buffers 60040 Read out the number of available Fifo buffersAnalog acquisition or generation boards Fifo Mode ProgrammingBuffer processing Digital I/O 701x or 702x or pattern generator boardsSpcfifostart Example Fifo generation mode== Maxbuf SpcfifowaitProgramming Internally generated sample rate Clock generationStandard internal sample rate External reference clock Using plain quartz with no PLLExternal clocking Minimum external sample rate Direct external clockMaximum external samplerate in MS/s Example External clock with dividerCHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 Software trigger Example for setting up the software triggerTrigger modes and appendant registers External TTL triggerTrigger modes and appendant registers Example on how to set up the board for positive TTL triggerEdge triggers Positive TTL triggerPositive and negative TTL trigger Output modes Standard ModeOption Multiple Replay Trigger modesResulting start delays Trigger modes Option Multiple ReplayOption Gated Replay General information and trigger delayOption Gated Replay Value Direction DescriptionExternal TTL edge trigger Example programAllowed trigger modes Spctriggermode TmttlposChannel direction Option Extra I/ODigital I/Os Transfer DataProgramming example Analog OutputsAnalog Outputs Option Extra I/O Synchronization with option cascading Synchronization OptionDifferent synchronization options Synchronization with option starhubExample of board setup for three boards Setup order for the different synchronization optionsSet up the board parameters Write Data to on-board memory output boards only3a Define synchronization or trigger Define the boards for trigger masterExample of board #2 set as trigger master Define the remaining boards as trigger slavesDefine the remaining boards as clock slaves Define the board for clock masterExample board number 0 is clock master Arm the boards for synchronizationRead data from the on-board memory acquisition boards only Start all of the trigger master boardsWait for the end of the measurement Example for data readingSpcsyncmasterfifo Allocate the Fifo software buffers2a Write first data for output boards SpcsyncslavefifoAs trigger slaves Calculating the clock dividers Additions for synchronizing different boardsGeneral information 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx40 MS/s Setting up the clock dividerBoard type 3122 3120 Board type 3025 3131Delay in Fifo mode Resulting delays using different boards or speedsDelay in standard non Fifo modes Additions for equal boards with different sample ratesAppendix Error CodesError name Value hex Value dec Error description AppendixExtra I/O with external connectorOption -XMF Pin assignment of the multipin connectorPin assignment of the multipin cable D14 D12 D10 Pin assignment of the internal multipin connectorExtra I/O with internal connector Option -XIO D15 D13 D11
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