Spectrum Brands MI.61XX manual Pin assignment of the multipin connector

Page 78

Pin assignment of the multipin connector

Pin assignment of the multipin connector

The 40 lead multipin connector is the main connector for all of Spectrum’s digital boards and is addi- tionally used for different options, like “Extra I/O“ or the additional digital inputs (on analog acquisition boards only) or additional digital outputs (on analog generation boards only).

The connectors for all the options are mounted on an extra bracket, while the main conncectors for the digital boards are mounted directly on the board’s bracket. Only in case that a digital board uses more than two connectors (more than 32 in and/or output bits) an additional bracket will be used for moun- ting the connectors as well.

The pin assignment depends on what type of board you have and on which of the below mentioned options are installed.

Extra I/O with external connector(Option -XMF)

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

D0

GND

D1

GND

D2

GND

D3

GND

D4

GND

D5

GND

D6

GND

D7

GND

n.c.

n.c.

n.c.

n.c.

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

D8

GND

D9

GND

D10

GND

D11

GND

D12

GND

D13

GND

D14

GND

D15

GND

n.c.

n.c.

n.c.

n.c.

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

B33

B34

B35

B36

B37

B38

B39

B40

D16

GND

D17

GND

D18

GND

D19

GND

D20

GND

D21

GND

D22

GND

D23

GND

n.c.

n.c.

n.c.

n.c.

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

A37

A38

A39

A40

A0

GND

GND

GND

A1

GND

GND

GND

A2

GND

GND

GND

A3

GND

GND

GND

n.c.

n.c.

n.c.

n.c.

A3…A0 are the pins for the analog outputs, while D23…D0 are the 24 digital I/Os.

Pin assignment of the multipin cable

The 40 lead multipin cable is used for the additional digital inputs (on analog acquisition boards only) or additional digital outputs (on analog generation boards only) as well as for the digital I/O or pat- tern generator boards.

The flat ribbon cable is shipped with the boards that are equipped with one or more of the above mentioned options. The cable ends are assembled with a standard IDC socket connector so you can ea- sily make connections to your type of equipment or DUT (device un- der test).

The pin assignment is given in the table in the according chapter of the appendix.

78	MI.61xx Manual

Image 78

Contents MI.61xx English version October 5Page Introduction Hardware InstallationSoftware Driver Installation SoftwareAnalog Outputs Fifo ModeProgramming the Board Standard generation modesSynchronization Option Option Gated ReplayOption Extra I/O AppendixGeneral Information IntroductionPreface PrefaceDifferent models of the MI.61xx series MI.6110 MI.6111Introduction Additional options Extra I/O Option -XMFExtra I/O Option -XIO Starhub Introduction Additional optionsSpectrum type plate Block diagram Technical Data Hardware informationHardware informationIntroduction Dynamic ParametersOrder information FilterHardware Installation Installing the board in the systemSystem Requirements Installing a board with digital inputs/outputs Installing a board with extra I/O Option -XMFHooking up the boards Installing multiple boards synchronized by starhubMounting the wired boards Only use the included flat ribbon cablesInstalling multiple synchronized boards Software Driver Installation Software Driver InstallationInterrupt Sharing Installation WindowsVersion control Driver Update Windows Software Driver Installation Windows Windows XP Windows XP Windows NT Adding boards to the Windows NT driverLinux OverviewDriver info Installing the deviceNow it is possible to access the board using this device Automatic load of the driverFirst Test with SBench SoftwareSoftware Overview SoftwareMicrosoft Visual C++ ++ Driver InterfaceHeader files Linux Gnu CDriver functions Other Windows C/C++ compilersNational Instruments LabWindows/CVI Include DriversFunction SpcSetData Windows Function SpcSetParamFunction SpcSetParam Function SpcGetDataSpectrum GmbH Include Driver Delphi Pascal Programming InterfaceType definition ExamplesDelphi Pascal Programming Interface Visual Basic Programming Interface Visual Basic ExamplesVBA for Excel Examples Visual Basic Programming Interface Overview Error handlingProgramming the Board Register tablesStarting the automatic initialization routine Example for error checkingInitialization PCI RegisterDate of production Installed memoryHardware version Serial numberUsed type of driver Installed features and optionsUsed interrupt line Driver versionSpcpcimemsize Powerdown and resetExample program for the board initialization SpcpciserialnoImportant note on channels selection Analog OutputsChannel Selection Disabling the outputsOutput offset Setting up the outputsOutput Amplifiers Register Value Direction Description Amplitude rangeFilter Specifications Maximum Output RangeOutput Filters Standard generation modes General descriptionProgramming Maximum posttrigger in MSamples Standard generation modes ProgrammingMaximum memsize Minimum and stepsize of memsize and posttrigger in samplesCommand register Starting without interrupt classic modeStarting with interrupt driven mode ProgrammingStandard generation modesValue ’start’ as a 32 bit integer value Data organizationWriting data with SpcSetData Value ’len’ as a 32 bit integer valueStandard mode Bit Standard ModeSample format Background Fifo Write Fifo ModeGeneral Information Speed LimitationsTheoretical maximum sample rate PCI Bus Throughput Programming Fifo ModeSoftware Buffers 60040 Read out the number of available Fifo buffersAnalog acquisition or generation boards Fifo Mode ProgrammingBuffer processing Digital I/O 701x or 702x or pattern generator boardsSpcfifostart Example Fifo generation mode== Maxbuf SpcfifowaitProgramming Clock generation Internally generated sample rateStandard internal sample rate Using plain quartz with no PLL External reference clockExternal clocking Direct external clock Minimum external sample rateMaximum external samplerate in MS/s External clock with divider ExampleCHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 Software trigger Example for setting up the software triggerTrigger modes and appendant registers External TTL triggerTrigger modes and appendant registers Example on how to set up the board for positive TTL triggerEdge triggers Positive TTL triggerPositive and negative TTL trigger Output modes Standard ModeOption Multiple Replay Trigger modesResulting start delays Trigger modes Option Multiple ReplayOption Gated Replay General information and trigger delayOption Gated Replay Value Direction DescriptionExternal TTL edge trigger Example programAllowed trigger modes Spctriggermode TmttlposChannel direction Option Extra I/ODigital I/Os Transfer DataAnalog Outputs Programming exampleAnalog Outputs Option Extra I/O Synchronization with option cascading Synchronization OptionDifferent synchronization options Synchronization with option starhubExample of board setup for three boards Setup order for the different synchronization optionsSet up the board parameters Write Data to on-board memory output boards only3a Define synchronization or trigger Define the boards for trigger masterExample of board #2 set as trigger master Define the remaining boards as trigger slavesDefine the remaining boards as clock slaves Define the board for clock masterExample board number 0 is clock master Arm the boards for synchronizationRead data from the on-board memory acquisition boards only Start all of the trigger master boardsWait for the end of the measurement Example for data readingSpcsyncmasterfifo Allocate the Fifo software buffers2a Write first data for output boards SpcsyncslavefifoAs trigger slaves Calculating the clock dividers Additions for synchronizing different boardsGeneral information 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx40 MS/s Setting up the clock dividerBoard type 3122 3120 Board type 3025 3131Delay in Fifo mode Resulting delays using different boards or speedsDelay in standard non Fifo modes Additions for equal boards with different sample ratesAppendix Error CodesError name Value hex Value dec Error description AppendixPin assignment of the multipin connector Extra I/O with external connectorOption -XMFPin assignment of the multipin cable D14 D12 D10 Pin assignment of the internal multipin connectorExtra I/O with internal connector Option -XIO D15 D13 D11