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Arm Enterprises IM-AD1 manual Stepper motor connectors, Stepper motor interface signals

Models: IM-AD1

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Hardware Reference

			Table 3-6 Stepper motor interface signals (continued)

	Signal	EXPB		Description
	Signal	connector		Description
		connector

	STEP2_PH1	F8		Step2 phase 1 drive signal

	STEP2_PH2	F9		Step2 phase 2 drive signal

	STEP2_PH3	F10		Step2 phase 3 drive signal

	STEP2_PH4	F11		Step2 phase 4 drive signal

	STEP3_ENA	F12		Enable signal for STEP3_O1 and STEP3_O2

	STEP3_ENB	F13		Enable signal for STEP3_O3 and STEP3_O4

	STEP3_PH1	F14		Step3 phase 1 drive signal

	STEP3_PH2	F15		Step3 phase 2 drive signal

	STEP3_PH3	F16		Step3 phase 3 drive signal

	STEP3_PH4	F17		Step3 phase 4 drive signal

	STEP4_ENA	F18		Enable signal for STEP4_O1 and STEP4_O2

	STEP4_ENB	F19		Enable signal for STEP4_O3 and STEP4_O4

	STEP4_PH1	F20		Step4 phase 1 drive signal

	STEP4_PH2	F21		Step4 phase 2 drive signal

	STEP4_PH3	F22		Step4 phase 3 drive signal

	STEP4_PH4	F23		Step4 phase 4 drive signal

3.5.3Stepper motor connectors

Figure 3-6shows the pin numbering of the stepper motor connectors.

1

2

3

4

5

6

Figure 3-6 Stepper motor connector (J19/J23)

3-10

Copyright © 2001-2003. All rights reserved.

ARM DUI 0163B

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Arm Enterprises IM-AD1 manual Stepper motor connectors, Stepper motor interface signals

Contents

Integrator/IM-AD1 Integrator/IM-AD1 User GuideConformance Notices Copyright 2001-2003. All rights reserved Integrator/IM-AD1 User Guide Chapter IntroductionAppendix a Signal Descriptions Preface About this book Using this bookIntended audience Further reading Typographical conventionsARM publications Third-party documents Feedback on this document FeedbackFeedback on the Integrator/IM-AD1 Xii Introduction About the Integrator/IM-AD1 ARM DUI 0163BIntegrator/IM-AD1 layout Interface module features and architecture FeaturesIntegrator/IM-AD1 block diagram ArchitectureConfig LED Links and LEDsCare of modules Introduction Copyright 2001-2003. All rights reserved Getting Started Fitting the interface module Assembled Integrator development systemSetting up the logic module Switch 2 Closed Switch 3 Open Switch 4 OpenRunning the test software Hardware Reference Hardware Reference Uart interface Serial interface signal assignment Signal nameConnector DescriptionSerial connector pinout Serial connector signal assignment Pin J18 Type DescriptionSPI signals Signal SPIPWM interface signals Signal PWM interfaceShows the signal assignment PWM connector signals Pin J14 J10 DescriptionStepper motor interface Functional descriptionStepper motor interface signal summary Therefore, with a 0.1Ω sense resistor fittedStepper motor connectors Stepper motor interface signalsStepper motor connector signals Pin J19 J23 Description VSSGpio connectors J16 and J17 GpioHardware Reference U13 Can interfaceBuffer Can interface signal assignment Signal IMBBANK29 IMBBANK28IMBBANK30 Can connector signal assignments Pin GNDADC and DAC interfaces 10 ADC and DAC interface architectureIMABANK50 IMABANK48IMABANK49 IMABANK5111shows the pinout of the ADC interface connector J1 12 shows the pinout of the DAC interface connector J2 Hardware Reference Copyright 2001-2003. All rights reserved Reference Design Example About PrimeCells About the design exampleExample architecture Vhdl file descriptions File DescriptionExample memory map Address assignment of logic modules Integrator system memory mapLogic module addresses Position Bits Stack Integrator/IM-AD1 memory mapIntegrator/IM-AD1 memory map Device Address Gpiob StepperbGpioa SsramLogic module registers Example APB register peripheralOffset address Name Type Function Oscillator divisor registers RDW LMOSCx registers Bits Name Access FunctionVDW User LEDs control register Bits Name Access FunctionOscillator lock register Push button interrupt registerSwitches register Uart SPICS1 SPI chip select registerSPICS2 SPICS0Synchronous serial port PWM controller Cont Offset Name Access Function AddressStepper motor peripheral CountStepper x control register Singlestep DocountDIR Stepx count register Stepx speed registerData output set register Read data output pinsAddress offset Name Access Size Function Read data input registerData direction Gpio direction control 1 bitSsram interface Interrupt Interrupt source Source number Vectored interrupt controllerInterrupt sources CAN1Reference Design Example Can controller interface Can reset control registerCanreset CANxBaseAdcstatus ADC and DAC interface16 ADC and DAC interface registers ADC2BUSY18 PIB entry format Peripheral information blockBits Name Function Signal Descriptions Expa Table A-1 AHB signal assignment Pin label Signal DescriptionExpb Table A-2 Expb signal description Pin label Name DescriptionExpim Label Table A-3 Expim signal descriptionsLM-EP20K1000E Description Logic analyzer connector Figure A-4 J7 pin locationsTable A-4 J7 connector pinout Signal Pin CLK1Figure A-5 Multi-ICE connector pinout Multi-ICE JtagMechanical Specification Figure B-1 Board dimensions top view Mechanical informationFigure B-2 Bottom board dimensions viewed from top side DB9DUAL Connector referenceDB9STRAIGHT FCI Glossary Multi-ICESynchronous Serial Port DAC IndexADC Can GpioGpiodataclr Gpiodatain Gpiodataout Gpiodataset Gpiodirn Expa A-2Lmleds Lmlock LMOSC1