Arm Enterprises IM-AD1 guide

Hardware Reference

The analog inputs to the ADCs are buffered by LMV324 operational amplifiers (op-amps). The op-amps are configured to give unity gain but the inputs have a resistive divider that divides the input voltage by 2. A 0-5V input signal range at the buffer inputs provides a 0-2.5V full range at the ADC input. If different input ranges are required the divider resistor values can be changed.

The op-amp buffers cannot drive their outputs lower than 65mV. This means input signals less than 130mV will have incorrect ADC values.

The reference voltage from one of the ADCs is buffered and fed to the reference inputs of the other ADC and the DAC so that all devices share a common reference. The GAIN input to the DAC is tied HIGH to configure the output range of the DAC to be 0 to 2xVref.

Figure 3-11shows the pinout of the ADC interface connector (J1).

						J1
5V

					1			2

ADC0


ADC1


ADC2


ADC3


ADC4


ADC5


ADC6


ADC7



ADC8



ADC9


ADC10


ADC11


ADC12


ADC13


ADC14


ADC15



					33			34

5V GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

Figure 3-11 ADC connector pinout

3-20

Copyright © 2001-2003. All rights reserved.

ARM DUI 0163B

Image 44

Arm Enterprises IM-AD1 manual 11shows the pinout of the ADC interface connector J1

Contents

Integrator/IM-AD1 Integrator/IM-AD1 User Guide Conformance Notices Copyright 2001-2003. All rights reserved Integrator/IM-AD1 User Guide Chapter Introduction Appendix a Signal Descriptions Preface Intended audience Using this bookAbout this book ARM publications Typographical conventionsFurther reading Third-party documents Feedback on the Integrator/IM-AD1 FeedbackFeedback on this document Xii Introduction About the Integrator/IM-AD1 ARM DUI 0163B Integrator/IM-AD1 layout Interface module features and architecture Features Integrator/IM-AD1 block diagram Architecture Config LED Links and LEDs Care of modules Introduction Copyright 2001-2003. All rights reserved Getting Started Fitting the interface module Assembled Integrator development system Setting up the logic module Switch 2 Closed Switch 3 Open Switch 4 Open Running the test software Hardware Reference Hardware Reference Serial interface signal assignment Signal name ConnectorUart interface Description Serial connector pinout Serial connector signal assignment Pin J18 Type Description SPI signals Signal SPI PWM interface signals Signal PWM interface Shows the signal assignment PWM connector signals Pin J14 J10 Description Stepper motor interface Functional description Stepper motor interface signal summary Therefore, with a 0.1Ω sense resistor fitted Stepper motor connectors Stepper motor interface signals Stepper motor connector signals Pin J19 J23 Description VSS Gpio connectors J16 and J17 Gpio Hardware Reference Buffer Can interfaceU13 Can interface signal assignment Signal IMBBANK30 IMBBANK28IMBBANK29 Can connector signal assignments Pin GND ADC and DAC interfaces 10 ADC and DAC interface architecture IMABANK48 IMABANK49IMABANK50 IMABANK51 11shows the pinout of the ADC interface connector J1 12 shows the pinout of the DAC interface connector J2 Hardware Reference Copyright 2001-2003. All rights reserved Reference Design Example Example architecture About the design exampleAbout PrimeCells Vhdl file descriptions File Description Example memory map Address assignment of logic modules Integrator system memory map Integrator/IM-AD1 memory map Device Address Integrator/IM-AD1 memory mapLogic module addresses Position Bits Stack Stepperb GpioaGpiob Ssram Offset address Name Type Function Example APB register peripheralLogic module registers Oscillator divisor registers VDW LMOSCx registers Bits Name Access FunctionRDW Bits Name Access Function Oscillator lock registerUser LEDs control register Push button interrupt register Switches register Uart SPI chip select register SPICS2SPICS1 SPICS0 Synchronous serial port PWM controller Offset Name Access Function Address Stepper motor peripheralCont Count Stepper x control register DIR DocountSinglestep Stepx count register Stepx speed register Read data output pins Address offset Name Access Size FunctionData output set register Read data input register Data direction Gpio direction control 1 bit Ssram interface Vectored interrupt controller Interrupt sourcesInterrupt Interrupt source Source number CAN1 Reference Design Example Can reset control register CanresetCan controller interface CANxBase ADC and DAC interface 16 ADC and DAC interface registersAdcstatus ADC2BUSY Bits Name Function Peripheral information block18 PIB entry format Signal Descriptions Expa Table A-1 AHB signal assignment Pin label Signal Description Expb Table A-2 Expb signal description Pin label Name Description Expim LM-EP20K1000E Description Table A-3 Expim signal descriptionsLabel Logic analyzer connector Figure A-4 J7 pin locations Table A-4 J7 connector pinout Signal Pin CLK1 Figure A-5 Multi-ICE connector pinout Multi-ICE Jtag Mechanical Specification Figure B-1 Board dimensions top view Mechanical information Figure B-2 Bottom board dimensions viewed from top side DB9STRAIGHT FCI Connector referenceDB9DUAL Glossary Multi-ICE Synchronous Serial Port Index ADC CanDAC Gpio Lmleds Lmlock LMOSC1 Expa A-2Gpiodataclr Gpiodatain Gpiodataout Gpiodataset Gpiodirn