Logic analyzer connector | Arm Enterprises IM-AD1 specification

Signal Descriptions

A.4 Logic analyzer connector

A Mictor-type logic analyzer connector is provided. It connects to the B[31:0] signals used for GPIO B. If particular signals must be connected to a logic analyzer, the FPGA configuration can be changed to reassign the signal connections.

Caution

If the FPGA configuration is changed to reassign signal connections, the GPIO B connections on connector J16 also change.

Figure A-4 shows the pin numbers of this type of connector.

1

2

37

38

Figure A-4 J7 pin locations

A-8

Copyright © 2001-2003. All rights reserved.

ARM DUI 0163B

Image 82

Arm Enterprises IM-AD1 manual Logic analyzer connector, Figure A-4 J7 pin locations

Contents

Integrator/IM-AD1 Integrator/IM-AD1 User Guide Conformance Notices Copyright 2001-2003. All rights reserved Integrator/IM-AD1 User Guide Chapter Introduction Appendix a Signal Descriptions Preface About this book Using this bookIntended audience Further reading Typographical conventionsARM publications Third-party documents Feedback on this document FeedbackFeedback on the Integrator/IM-AD1 Xii Introduction About the Integrator/IM-AD1 ARM DUI 0163B Integrator/IM-AD1 layout Interface module features and architecture Features Integrator/IM-AD1 block diagram Architecture Config LED Links and LEDs Care of modules Introduction Copyright 2001-2003. All rights reserved Getting Started Fitting the interface module Assembled Integrator development system Setting up the logic module Switch 2 Closed Switch 3 Open Switch 4 Open Running the test software Hardware Reference Hardware Reference Uart interface Serial interface signal assignment Signal nameConnector Description Serial connector pinout Serial connector signal assignment Pin J18 Type Description SPI signals Signal SPI PWM interface signals Signal PWM interface Shows the signal assignment PWM connector signals Pin J14 J10 Description Stepper motor interface Functional description Stepper motor interface signal summary Therefore, with a 0.1Ω sense resistor fitted Stepper motor connectors Stepper motor interface signals Stepper motor connector signals Pin J19 J23 Description VSS Gpio connectors J16 and J17 Gpio Hardware Reference U13 Can interfaceBuffer Can interface signal assignment Signal IMBBANK29 IMBBANK28IMBBANK30 Can connector signal assignments Pin GND ADC and DAC interfaces 10 ADC and DAC interface architecture IMABANK50 IMABANK48IMABANK49 IMABANK51 11shows the pinout of the ADC interface connector J1 12 shows the pinout of the DAC interface connector J2 Hardware Reference Copyright 2001-2003. All rights reserved Reference Design Example About PrimeCells About the design exampleExample architecture Vhdl file descriptions File Description Example memory map Address assignment of logic modules Integrator system memory map Logic module addresses Position Bits Stack Integrator/IM-AD1 memory mapIntegrator/IM-AD1 memory map Device Address Gpiob StepperbGpioa Ssram Logic module registers Example APB register peripheralOffset address Name Type Function Oscillator divisor registers RDW LMOSCx registers Bits Name Access FunctionVDW User LEDs control register Bits Name Access FunctionOscillator lock register Push button interrupt register Switches register Uart SPICS1 SPI chip select registerSPICS2 SPICS0 Synchronous serial port PWM controller Cont Offset Name Access Function AddressStepper motor peripheral Count Stepper x control register Singlestep DocountDIR Stepx count register Stepx speed register Data output set register Read data output pinsAddress offset Name Access Size Function Read data input register Data direction Gpio direction control 1 bit Ssram interface Interrupt Interrupt source Source number Vectored interrupt controllerInterrupt sources CAN1 Reference Design Example Can controller interface Can reset control registerCanreset CANxBase Adcstatus ADC and DAC interface16 ADC and DAC interface registers ADC2BUSY 18 PIB entry format Peripheral information blockBits Name Function Signal Descriptions Expa Table A-1 AHB signal assignment Pin label Signal Description Expb Table A-2 Expb signal description Pin label Name Description Expim Label Table A-3 Expim signal descriptionsLM-EP20K1000E Description Logic analyzer connector Figure A-4 J7 pin locations Table A-4 J7 connector pinout Signal Pin CLK1 Figure A-5 Multi-ICE connector pinout Multi-ICE Jtag Mechanical Specification Figure B-1 Board dimensions top view Mechanical information Figure B-2 Bottom board dimensions viewed from top side DB9DUAL Connector referenceDB9STRAIGHT FCI Glossary Multi-ICE Synchronous Serial Port DAC IndexADC Can Gpio Gpiodataclr Gpiodatain Gpiodataout Gpiodataset Gpiodirn Expa A-2Lmleds Lmlock LMOSC1