Integrator/IM-AD1 memory map | Arm Enterprises specification

Reference Design Example

page 4-6shows the values of address bits [31:28] on logic modules fitted to an Integrator/AP in the EXPA/EXPB connector position (see the Integrator/AP User Guide for more information).

Table 4-2 Logic module addresses

	Position in		Bits 31:28
	stack		Bits 31:28
	stack

	0	(bottom)	0xC

	1		0xD

	2		0xE

	3	(top)	0xF

4.1.5Integrator/IM-AD1 memory map

The memory model for the design is shown in Table 4-2and assumes that the logic module is mounted in position 0.

Table 4-3 Integrator/IM-AD1 memory map

Device	Address

logic module APB registers	0xC0000000

UART0	0xC0100000

SPICS	0xC0200000

SSP	0xC0300000

Reserved	0xC0400000

Reserved	0xC0500000

Reserved	0xC0600000

Reserved	0xC0700000

Reserved	0xC0800000

Reserved	0xC0900000

DCDC	0xC0A00000

STEPPERA	0xC0B00000

4-6

Copyright © 2001-2003. All rights reserved.

ARM DUI 0163B

Image 52

Arm Enterprises manual Integrator/IM-AD1 memory map, Logic module addresses Position Bits Stack

Contents

Integrator/IM-AD1 Integrator/IM-AD1 User Guide Conformance Notices Copyright 2001-2003. All rights reserved Integrator/IM-AD1 User Guide Chapter Introduction Appendix a Signal Descriptions Preface About this book Using this bookIntended audience Further reading Typographical conventionsARM publications Third-party documents Feedback on this document FeedbackFeedback on the Integrator/IM-AD1 Xii Introduction About the Integrator/IM-AD1 ARM DUI 0163B Integrator/IM-AD1 layout Interface module features and architecture Features Integrator/IM-AD1 block diagram Architecture Config LED Links and LEDs Care of modules Introduction Copyright 2001-2003. All rights reserved Getting Started Fitting the interface module Assembled Integrator development system Setting up the logic module Switch 2 Closed Switch 3 Open Switch 4 Open Running the test software Hardware Reference Hardware Reference Serial interface signal assignment Signal name ConnectorUart interface Description Serial connector pinout Serial connector signal assignment Pin J18 Type Description SPI signals Signal SPI PWM interface signals Signal PWM interface Shows the signal assignment PWM connector signals Pin J14 J10 Description Stepper motor interface Functional description Stepper motor interface signal summary Therefore, with a 0.1Ω sense resistor fitted Stepper motor connectors Stepper motor interface signals Stepper motor connector signals Pin J19 J23 Description VSS Gpio connectors J16 and J17 Gpio Hardware Reference U13 Can interfaceBuffer Can interface signal assignment Signal IMBBANK29 IMBBANK28IMBBANK30 Can connector signal assignments Pin GND ADC and DAC interfaces 10 ADC and DAC interface architecture IMABANK48 IMABANK49IMABANK50 IMABANK51 11shows the pinout of the ADC interface connector J1 12 shows the pinout of the DAC interface connector J2 Hardware Reference Copyright 2001-2003. All rights reserved Reference Design Example About PrimeCells About the design exampleExample architecture Vhdl file descriptions File Description Example memory map Address assignment of logic modules Integrator system memory map Logic module addresses Position Bits Stack Integrator/IM-AD1 memory mapIntegrator/IM-AD1 memory map Device Address Stepperb GpioaGpiob Ssram Logic module registers Example APB register peripheralOffset address Name Type Function Oscillator divisor registers RDW LMOSCx registers Bits Name Access FunctionVDW Bits Name Access Function Oscillator lock registerUser LEDs control register Push button interrupt register Switches register Uart SPI chip select register SPICS2SPICS1 SPICS0 Synchronous serial port PWM controller Offset Name Access Function Address Stepper motor peripheralCont Count Stepper x control register Singlestep DocountDIR Stepx count register Stepx speed register Read data output pins Address offset Name Access Size FunctionData output set register Read data input register Data direction Gpio direction control 1 bit Ssram interface Vectored interrupt controller Interrupt sourcesInterrupt Interrupt source Source number CAN1 Reference Design Example Can reset control register CanresetCan controller interface CANxBase ADC and DAC interface 16 ADC and DAC interface registersAdcstatus ADC2BUSY 18 PIB entry format Peripheral information blockBits Name Function Signal Descriptions Expa Table A-1 AHB signal assignment Pin label Signal Description Expb Table A-2 Expb signal description Pin label Name Description Expim Label Table A-3 Expim signal descriptionsLM-EP20K1000E Description Logic analyzer connector Figure A-4 J7 pin locations Table A-4 J7 connector pinout Signal Pin CLK1 Figure A-5 Multi-ICE connector pinout Multi-ICE Jtag Mechanical Specification Figure B-1 Board dimensions top view Mechanical information Figure B-2 Bottom board dimensions viewed from top side DB9DUAL Connector referenceDB9STRAIGHT FCI Glossary Multi-ICE Synchronous Serial Port Index ADC CanDAC Gpio Gpiodataclr Gpiodatain Gpiodataout Gpiodataset Gpiodirn Expa A-2Lmleds Lmlock LMOSC1