Address assignment of logic modules | Arm Enterprises IM-AD1

Reference Design Example

0xF0000000

0xE0000000

0xD0000000

0xC0000000

Logic module 3

Logic module 2

Logic module 1

Logic module 0

Core module alias memory

PCI

Core module/ motherboard memory

and peripherals

AHB

peripherals

APB peripherals

0xCFFFFFFF

0xC1000000

0xC0000000

Figure 4-2 Integrator system memory map

Note

The Integrator system implements a distributed address decoding scheme in which each core or logic module is responsible for decoding its own address space. It is important when implementing a logic module design, to ensure that the module responds to all memory accesses in the appropriate memory region (see the user guide for your motherboard).

4.1.4Address assignment of logic modules

The Integrator motherboards can have more than one logic module mounted on them. The base address of each logic module depends on its position in the stack and defines the value of bits [31:28] of the address for all devices on the logic module. Table 4-2 on

ARM DUI 0163B

Copyright © 2001-2003. All rights reserved.

4-5

Image 51

Arm Enterprises IM-AD1 manual Address assignment of logic modules, Integrator system memory map

Contents

Integrator/IM-AD1 User Guide Integrator/IM-AD1 Conformance Notices Copyright 2001-2003. All rights reserved Chapter Introduction Integrator/IM-AD1 User Guide Appendix a Signal Descriptions Preface Using this book About this bookIntended audience Typographical conventions Further readingARM publications Third-party documents Feedback Feedback on this documentFeedback on the Integrator/IM-AD1 Xii Introduction ARM DUI 0163B About the Integrator/IM-AD1 Integrator/IM-AD1 layout Features Interface module features and architecture Architecture Integrator/IM-AD1 block diagram Links and LEDs Config LED Care of modules Introduction Copyright 2001-2003. All rights reserved Getting Started Assembled Integrator development system Fitting the interface module Switch 2 Closed Switch 3 Open Switch 4 Open Setting up the logic module Running the test software Hardware Reference Hardware Reference Description Serial interface signal assignment Signal nameConnector Uart interface Serial connector signal assignment Pin J18 Type Description Serial connector pinout SPI SPI signals Signal PWM interface PWM interface signals Signal PWM connector signals Pin J14 J10 Description Shows the signal assignment Functional description Stepper motor interface Therefore, with a 0.1Ω sense resistor fitted Stepper motor interface signal summary Stepper motor interface signals Stepper motor connectors VSS Stepper motor connector signals Pin J19 J23 Description Gpio Gpio connectors J16 and J17 Hardware Reference Can interface U13Buffer Can interface signal assignment Signal IMBBANK28 IMBBANK29IMBBANK30 GND Can connector signal assignments Pin 10 ADC and DAC interface architecture ADC and DAC interfaces IMABANK51 IMABANK48IMABANK49 IMABANK50 11shows the pinout of the ADC interface connector J1 12 shows the pinout of the DAC interface connector J2 Hardware Reference Copyright 2001-2003. All rights reserved Reference Design Example About the design example About PrimeCellsExample architecture File Description Vhdl file descriptions Example memory map Integrator system memory map Address assignment of logic modules Integrator/IM-AD1 memory map Logic module addresses Position Bits StackIntegrator/IM-AD1 memory map Device Address Ssram StepperbGpioa Gpiob Example APB register peripheral Logic module registersOffset address Name Type Function Oscillator divisor registers LMOSCx registers Bits Name Access Function RDWVDW Push button interrupt register Bits Name Access FunctionOscillator lock register User LEDs control register Switches register Uart SPICS0 SPI chip select registerSPICS2 SPICS1 Synchronous serial port PWM controller Count Offset Name Access Function AddressStepper motor peripheral Cont Stepper x control register Docount SinglestepDIR Stepx speed register Stepx count register Read data input register Read data output pinsAddress offset Name Access Size Function Data output set register Gpio direction control 1 bit Data direction Ssram interface CAN1 Vectored interrupt controllerInterrupt sources Interrupt Interrupt source Source number Reference Design Example CANxBase Can reset control registerCanreset Can controller interface ADC2BUSY ADC and DAC interface16 ADC and DAC interface registers Adcstatus Peripheral information block 18 PIB entry formatBits Name Function Signal Descriptions Expa Pin label Signal Description Table A-1 AHB signal assignment Expb Pin label Name Description Table A-2 Expb signal description Expim Table A-3 Expim signal descriptions LabelLM-EP20K1000E Description Figure A-4 J7 pin locations Logic analyzer connector CLK1 Table A-4 J7 connector pinout Signal Pin Multi-ICE Jtag Figure A-5 Multi-ICE connector pinout Mechanical Specification Mechanical information Figure B-1 Board dimensions top view Figure B-2 Bottom board dimensions viewed from top side Connector reference DB9DUALDB9STRAIGHT FCI Multi-ICE Glossary Synchronous Serial Port Gpio IndexADC Can DAC Expa A-2 Gpiodataclr Gpiodatain Gpiodataout Gpiodataset GpiodirnLmleds Lmlock LMOSC1