Vectored interrupt controller, CAN1, CAN2 | Arm Enterprises IM-AD1

Reference Design Example

4.10Vectored interrupt controller

The interrupt controller used in the example design is the Vectored Interrupt Controller (VIC) PrimeCell (PL190). Refer to the ARM PrimeCell Vectored Interrupt Controller (PL190) Technical Reference Manual for information about this device.

The assignment of interrupt sources to the VIC are shown in Table 4-13.

		Table 4-13 Interrupt assignment

	Interrupt		Interrupt source
	source number		Interrupt source
	source number

	0		LM_INT APB register

	1		UART0

	2		Reserved

	3		SSP

	4		STEP1 buffer empty

	5		STEP2 buffer empty

	6		STEP3 buffer empty

	7		STEP4 buffer empty

	8		CAN1

	9		CAN2

	10		ADC1 conversion complete

	11		ADC2 conversion complete

4.10.1Interrupt sources

The LM_INT interrupt comes from the push button interrupt register in the APB register block. The interrupt is latched if the push button on the logic module is pressed or if a 1 is written to the push button interrupt register. The interrupt is cleared by writing a 0 to the push button interrupt register.

The UART interrupt is the combined interrupt from the UART PrimeCell. Refer to ARM PrimeCell UART (PL011) Technical Reference Manual for details of the interrupt sources.

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ARM DUI 0163B

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Arm Enterprises IM-AD1 Vectored interrupt controller, Interrupt sources, Interrupt Interrupt source Source number, CAN1

Contents

Integrator/IM-AD1 Integrator/IM-AD1 User Guide Conformance Notices Copyright 2001-2003. All rights reserved Integrator/IM-AD1 User Guide Chapter Introduction Appendix a Signal Descriptions Preface About this book Using this bookIntended audience Further reading Typographical conventionsARM publications Third-party documents Feedback on this document FeedbackFeedback on the Integrator/IM-AD1 Xii Introduction About the Integrator/IM-AD1 ARM DUI 0163B Integrator/IM-AD1 layout Interface module features and architecture Features Integrator/IM-AD1 block diagram Architecture Config LED Links and LEDs Care of modules Introduction Copyright 2001-2003. All rights reserved Getting Started Fitting the interface module Assembled Integrator development system Setting up the logic module Switch 2 Closed Switch 3 Open Switch 4 Open Running the test software Hardware Reference Hardware Reference Uart interface Serial interface signal assignment Signal nameConnector Description Serial connector pinout Serial connector signal assignment Pin J18 Type Description SPI signals Signal SPI PWM interface signals Signal PWM interface Shows the signal assignment PWM connector signals Pin J14 J10 Description Stepper motor interface Functional description Stepper motor interface signal summary Therefore, with a 0.1Ω sense resistor fitted Stepper motor connectors Stepper motor interface signals Stepper motor connector signals Pin J19 J23 Description VSS Gpio connectors J16 and J17 Gpio Hardware Reference U13 Can interfaceBuffer Can interface signal assignment Signal IMBBANK29 IMBBANK28IMBBANK30 Can connector signal assignments Pin GND ADC and DAC interfaces 10 ADC and DAC interface architecture IMABANK50 IMABANK48IMABANK49 IMABANK51 11shows the pinout of the ADC interface connector J1 12 shows the pinout of the DAC interface connector J2 Hardware Reference Copyright 2001-2003. All rights reserved Reference Design Example About PrimeCells About the design exampleExample architecture Vhdl file descriptions File Description Example memory map Address assignment of logic modules Integrator system memory map Logic module addresses Position Bits Stack Integrator/IM-AD1 memory mapIntegrator/IM-AD1 memory map Device Address Gpiob StepperbGpioa Ssram Logic module registers Example APB register peripheralOffset address Name Type Function Oscillator divisor registers RDW LMOSCx registers Bits Name Access FunctionVDW User LEDs control register Bits Name Access FunctionOscillator lock register Push button interrupt register Switches register Uart SPICS1 SPI chip select registerSPICS2 SPICS0 Synchronous serial port PWM controller Cont Offset Name Access Function AddressStepper motor peripheral Count Stepper x control register Singlestep DocountDIR Stepx count register Stepx speed register Data output set register Read data output pinsAddress offset Name Access Size Function Read data input register Data direction Gpio direction control 1 bit Ssram interface Interrupt Interrupt source Source number Vectored interrupt controllerInterrupt sources CAN1 Reference Design Example Can controller interface Can reset control registerCanreset CANxBase Adcstatus ADC and DAC interface16 ADC and DAC interface registers ADC2BUSY 18 PIB entry format Peripheral information blockBits Name Function Signal Descriptions Expa Table A-1 AHB signal assignment Pin label Signal Description Expb Table A-2 Expb signal description Pin label Name Description Expim Label Table A-3 Expim signal descriptionsLM-EP20K1000E Description Logic analyzer connector Figure A-4 J7 pin locations Table A-4 J7 connector pinout Signal Pin CLK1 Figure A-5 Multi-ICE connector pinout Multi-ICE Jtag Mechanical Specification Figure B-1 Board dimensions top view Mechanical information Figure B-2 Bottom board dimensions viewed from top side DB9DUAL Connector referenceDB9STRAIGHT FCI Glossary Multi-ICE Synchronous Serial Port DAC IndexADC Can Gpio Gpiodataclr Gpiodatain Gpiodataout Gpiodataset Gpiodirn Expa A-2Lmleds Lmlock LMOSC1