Can controller interface, CANxBase | Arm Enterprises IM-AD1 specification

Reference Design Example

4.11CAN controller interface

The CAN controller interface gives you access to the internal registers and reset signals of the Bosch CC770 CAN controllers. The offset addresses of CAN controller interfaces are shown in Table 4-14.

			Table 4-14 CAN controller interface registers

	Offset	Name	Function
	address	Name	Function
	address

	0x000000	CAN1Base	Interface to CAN1 controller registers

	0x100000	CAN2Base	Interface to CAN2 controller registers

	0x200000	CANRESET	CAN reset control register

4.11.1CANxBase

You use the register interface locations to read and write the CAN registers. Register accesses take at least six system bus clock cycles and can be stretched by the CAN controller to a maximum of 550ns plus three system clock cycles.

The address pins CAN_A[7:0] of the CAN controllers are connected to HADDR[9:2]. This means that individual CAN registers are located on word boundaries starting from the base address of the device.

4.11.2CAN reset control register

The CAN reset register controls the nRESET signals to the CAN controllers. The assignment of the bits in the register is shown in Table 4-15.

Table 4-15 CAN reset register bit assignment

Bit	Name	Access	Function

1	CAN2nRESET	Read/write	Controls the nRESET signal to CAN2.

0	CAN1nRESET	Read/write	Controls the nRESET signal to CAN1.

The CAN controllers are reset by writing a 0 to the associated bit so the nRESET signal goes LOW. The default setting of this register after power up is 0, so you must write a 1 before you can read and write the internal registers of the CAN controllers. However, after power up the CAN resets must be held LOW for at least 1ms.

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Copyright © 2001-2003. All rights reserved.

ARM DUI 0163B

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Arm Enterprises IM-AD1 manual Can controller interface, CANxBase, Can reset control register, Offset Name Function Address

Contents

Integrator/IM-AD1 Integrator/IM-AD1 User Guide Conformance Notices Copyright 2001-2003. All rights reserved Integrator/IM-AD1 User Guide Chapter Introduction Appendix a Signal Descriptions Preface Using this book About this bookIntended audience Typographical conventions Further readingARM publications Third-party documents Feedback Feedback on this documentFeedback on the Integrator/IM-AD1 Xii Introduction About the Integrator/IM-AD1 ARM DUI 0163B Integrator/IM-AD1 layout Interface module features and architecture Features Integrator/IM-AD1 block diagram Architecture Config LED Links and LEDs Care of modules Introduction Copyright 2001-2003. All rights reserved Getting Started Fitting the interface module Assembled Integrator development system Setting up the logic module Switch 2 Closed Switch 3 Open Switch 4 Open Running the test software Hardware Reference Hardware Reference Serial interface signal assignment Signal name ConnectorUart interface Description Serial connector pinout Serial connector signal assignment Pin J18 Type Description SPI signals Signal SPI PWM interface signals Signal PWM interface Shows the signal assignment PWM connector signals Pin J14 J10 Description Stepper motor interface Functional description Stepper motor interface signal summary Therefore, with a 0.1Ω sense resistor fitted Stepper motor connectors Stepper motor interface signals Stepper motor connector signals Pin J19 J23 Description VSS Gpio connectors J16 and J17 Gpio Hardware Reference Can interface U13Buffer Can interface signal assignment Signal IMBBANK28 IMBBANK29IMBBANK30 Can connector signal assignments Pin GND ADC and DAC interfaces 10 ADC and DAC interface architecture IMABANK48 IMABANK49IMABANK50 IMABANK51 11shows the pinout of the ADC interface connector J1 12 shows the pinout of the DAC interface connector J2 Hardware Reference Copyright 2001-2003. All rights reserved Reference Design Example About the design example About PrimeCellsExample architecture Vhdl file descriptions File Description Example memory map Address assignment of logic modules Integrator system memory map Integrator/IM-AD1 memory map Logic module addresses Position Bits StackIntegrator/IM-AD1 memory map Device Address Stepperb GpioaGpiob Ssram Example APB register peripheral Logic module registersOffset address Name Type Function Oscillator divisor registers LMOSCx registers Bits Name Access Function RDWVDW Bits Name Access Function Oscillator lock registerUser LEDs control register Push button interrupt register Switches register Uart SPI chip select register SPICS2SPICS1 SPICS0 Synchronous serial port PWM controller Offset Name Access Function Address Stepper motor peripheralCont Count Stepper x control register Docount SinglestepDIR Stepx count register Stepx speed register Read data output pins Address offset Name Access Size FunctionData output set register Read data input register Data direction Gpio direction control 1 bit Ssram interface Vectored interrupt controller Interrupt sourcesInterrupt Interrupt source Source number CAN1 Reference Design Example Can reset control register CanresetCan controller interface CANxBase ADC and DAC interface 16 ADC and DAC interface registersAdcstatus ADC2BUSY Peripheral information block 18 PIB entry formatBits Name Function Signal Descriptions Expa Table A-1 AHB signal assignment Pin label Signal Description Expb Table A-2 Expb signal description Pin label Name Description Expim Table A-3 Expim signal descriptions LabelLM-EP20K1000E Description Logic analyzer connector Figure A-4 J7 pin locations Table A-4 J7 connector pinout Signal Pin CLK1 Figure A-5 Multi-ICE connector pinout Multi-ICE Jtag Mechanical Specification Figure B-1 Board dimensions top view Mechanical information Figure B-2 Bottom board dimensions viewed from top side Connector reference DB9DUALDB9STRAIGHT FCI Glossary Multi-ICE Synchronous Serial Port Index ADC CanDAC Gpio Expa A-2 Gpiodataclr Gpiodatain Gpiodataout Gpiodataset GpiodirnLmleds Lmlock LMOSC1