Spi, SPI signals Signal | Arm Enterprises IM-AD1 guide

Hardware Reference

3.3SPI

This interface module provides two connectors for SPI ports. They are connected directly to the logic module FPGA and are used by the SSP PrimeCell (PL022) in the example configuration.

Table 3-3 shows the assignment of the SPI signals to the logic module signals on the EXPIM connector.

Table 3-3 SPI signals

	Signal	EXPIM	Description
	Signal	connector	Description
		connector

	SPI_CLK	IM_BBANK31	SPI Clock

	SPI_TXD	IM_BBANK32	SPI transmit data

	SPI_RXD	IM_BBANK33	SPI receive data

	SPI_nCS0	IM_BBANK34	SPI chip select 0

	SPI_nCS1	IM_BBANK35	SPI chip select 1

	SPI_nCS2	IM_BBANK36	SPI chip select 2

Three chip select signals are provided to allow connection of three separate SPI devices. The SPI signals are routed to two connectors, J11 and J13, for ease of connection to different SPI devices, although both are connected to the same set of signals.

Figure 3-3 shows the pinout of the SPI connectors.

SPI_CLK

SPI_TXD

SPI_RXD

SPI_nCS0

SPI_nCS1

J11/J13

1 2

9 10

GND

+5V

+3V3

GND

SPI_nCS2

Figure 3-3 SPI interface connector pinout

ARM DUI 0163B

Copyright © 2001-2003. All rights reserved.

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Arm Enterprises IM-AD1 manual Spi, SPI signals Signal

Contents

Integrator/IM-AD1 User Guide Integrator/IM-AD1 Conformance Notices Copyright 2001-2003. All rights reserved Chapter Introduction Integrator/IM-AD1 User Guide Appendix a Signal Descriptions Preface Intended audience Using this bookAbout this book ARM publications Typographical conventionsFurther reading Third-party documents Feedback on the Integrator/IM-AD1 FeedbackFeedback on this document Xii Introduction ARM DUI 0163B About the Integrator/IM-AD1 Integrator/IM-AD1 layout Features Interface module features and architecture Architecture Integrator/IM-AD1 block diagram Links and LEDs Config LED Care of modules Introduction Copyright 2001-2003. All rights reserved Getting Started Assembled Integrator development system Fitting the interface module Switch 2 Closed Switch 3 Open Switch 4 Open Setting up the logic module Running the test software Hardware Reference Hardware Reference Connector Serial interface signal assignment Signal nameUart interface Description Serial connector signal assignment Pin J18 Type Description Serial connector pinout SPI SPI signals Signal PWM interface PWM interface signals Signal PWM connector signals Pin J14 J10 Description Shows the signal assignment Functional description Stepper motor interface Therefore, with a 0.1Ω sense resistor fitted Stepper motor interface signal summary Stepper motor interface signals Stepper motor connectors VSS Stepper motor connector signals Pin J19 J23 Description Gpio Gpio connectors J16 and J17 Hardware Reference Buffer Can interfaceU13 Can interface signal assignment Signal IMBBANK30 IMBBANK28IMBBANK29 GND Can connector signal assignments Pin 10 ADC and DAC interface architecture ADC and DAC interfaces IMABANK49 IMABANK48IMABANK50 IMABANK51 11shows the pinout of the ADC interface connector J1 12 shows the pinout of the DAC interface connector J2 Hardware Reference Copyright 2001-2003. All rights reserved Reference Design Example Example architecture About the design exampleAbout PrimeCells File Description Vhdl file descriptions Example memory map Integrator system memory map Address assignment of logic modules Integrator/IM-AD1 memory map Device Address Integrator/IM-AD1 memory mapLogic module addresses Position Bits Stack Gpioa StepperbGpiob Ssram Offset address Name Type Function Example APB register peripheralLogic module registers Oscillator divisor registers VDW LMOSCx registers Bits Name Access FunctionRDW Oscillator lock register Bits Name Access FunctionUser LEDs control register Push button interrupt register Switches register Uart SPICS2 SPI chip select registerSPICS1 SPICS0 Synchronous serial port PWM controller Stepper motor peripheral Offset Name Access Function AddressCont Count Stepper x control register DIR DocountSinglestep Stepx speed register Stepx count register Address offset Name Access Size Function Read data output pinsData output set register Read data input register Gpio direction control 1 bit Data direction Ssram interface Interrupt sources Vectored interrupt controllerInterrupt Interrupt source Source number CAN1 Reference Design Example Canreset Can reset control registerCan controller interface CANxBase 16 ADC and DAC interface registers ADC and DAC interfaceAdcstatus ADC2BUSY Bits Name Function Peripheral information block18 PIB entry format Signal Descriptions Expa Pin label Signal Description Table A-1 AHB signal assignment Expb Pin label Name Description Table A-2 Expb signal description Expim LM-EP20K1000E Description Table A-3 Expim signal descriptionsLabel Figure A-4 J7 pin locations Logic analyzer connector CLK1 Table A-4 J7 connector pinout Signal Pin Multi-ICE Jtag Figure A-5 Multi-ICE connector pinout Mechanical Specification Mechanical information Figure B-1 Board dimensions top view Figure B-2 Bottom board dimensions viewed from top side DB9STRAIGHT FCI Connector referenceDB9DUAL Multi-ICE Glossary Synchronous Serial Port ADC Can IndexDAC Gpio Lmleds Lmlock LMOSC1 Expa A-2Gpiodataclr Gpiodatain Gpiodataout Gpiodataset Gpiodirn