Uart | Arm Enterprises IM-AD1 guide

Reference Design Example

4.3UART

The UART used in the design example is the PrimeCell PL011. Refer to the ARM

PrimeCell UART (PL011) Technical Reference Manual for more information.

The UART is clocked by the signal CLK2 from the logic module. CLK2 is set to 12MHz by default.

ARM DUI 0163B

Copyright © 2001-2003. All rights reserved.

4-13

Image 59

Arm Enterprises IM-AD1 manual Uart

Contents

Integrator/IM-AD1 User Guide Integrator/IM-AD1 Conformance Notices Copyright 2001-2003. All rights reserved Chapter Introduction Integrator/IM-AD1 User Guide Appendix a Signal Descriptions Preface Intended audience Using this bookAbout this book ARM publications Typographical conventionsFurther reading Third-party documents Feedback on the Integrator/IM-AD1 FeedbackFeedback on this document Xii Introduction ARM DUI 0163B About the Integrator/IM-AD1 Integrator/IM-AD1 layout Features Interface module features and architecture Architecture Integrator/IM-AD1 block diagram Links and LEDs Config LED Care of modules Introduction Copyright 2001-2003. All rights reserved Getting Started Assembled Integrator development system Fitting the interface module Switch 2 Closed Switch 3 Open Switch 4 Open Setting up the logic module Running the test software Hardware Reference Hardware Reference Description Serial interface signal assignment Signal nameConnector Uart interface Serial connector signal assignment Pin J18 Type Description Serial connector pinout SPI SPI signals Signal PWM interface PWM interface signals Signal PWM connector signals Pin J14 J10 Description Shows the signal assignment Functional description Stepper motor interface Therefore, with a 0.1Ω sense resistor fitted Stepper motor interface signal summary Stepper motor interface signals Stepper motor connectors VSS Stepper motor connector signals Pin J19 J23 Description Gpio Gpio connectors J16 and J17 Hardware Reference Buffer Can interfaceU13 Can interface signal assignment Signal IMBBANK30 IMBBANK28IMBBANK29 GND Can connector signal assignments Pin 10 ADC and DAC interface architecture ADC and DAC interfaces IMABANK51 IMABANK48IMABANK49 IMABANK50 11shows the pinout of the ADC interface connector J1 12 shows the pinout of the DAC interface connector J2 Hardware Reference Copyright 2001-2003. All rights reserved Reference Design Example Example architecture About the design exampleAbout PrimeCells File Description Vhdl file descriptions Example memory map Integrator system memory map Address assignment of logic modules Integrator/IM-AD1 memory map Device Address Integrator/IM-AD1 memory mapLogic module addresses Position Bits Stack Ssram StepperbGpioa Gpiob Offset address Name Type Function Example APB register peripheralLogic module registers Oscillator divisor registers VDW LMOSCx registers Bits Name Access FunctionRDW Push button interrupt register Bits Name Access FunctionOscillator lock register User LEDs control register Switches register Uart SPICS0 SPI chip select registerSPICS2 SPICS1 Synchronous serial port PWM controller Count Offset Name Access Function AddressStepper motor peripheral Cont Stepper x control register DIR DocountSinglestep Stepx speed register Stepx count register Read data input register Read data output pinsAddress offset Name Access Size Function Data output set register Gpio direction control 1 bit Data direction Ssram interface CAN1 Vectored interrupt controllerInterrupt sources Interrupt Interrupt source Source number Reference Design Example CANxBase Can reset control registerCanreset Can controller interface ADC2BUSY ADC and DAC interface16 ADC and DAC interface registers Adcstatus Bits Name Function Peripheral information block18 PIB entry format Signal Descriptions Expa Pin label Signal Description Table A-1 AHB signal assignment Expb Pin label Name Description Table A-2 Expb signal description Expim LM-EP20K1000E Description Table A-3 Expim signal descriptionsLabel Figure A-4 J7 pin locations Logic analyzer connector CLK1 Table A-4 J7 connector pinout Signal Pin Multi-ICE Jtag Figure A-5 Multi-ICE connector pinout Mechanical Specification Mechanical information Figure B-1 Board dimensions top view Figure B-2 Bottom board dimensions viewed from top side DB9STRAIGHT FCI Connector referenceDB9DUAL Multi-ICE Glossary Synchronous Serial Port Gpio IndexADC Can DAC Lmleds Lmlock LMOSC1 Expa A-2Gpiodataclr Gpiodatain Gpiodataout Gpiodataset Gpiodirn