Can interface, U13, Buffer | Arm Enterprises IM-AD1 specs

Hardware Reference

3.7CAN interface

The IM-AD1 has two CAN interfaces provided by Bosch CC770 serial communications controllers. The network interfaces are provided by Philips TJA1050 transceivers, each capable of 1Mb/s data transfer.

Figure 3-8shows the architecture of the CAN interface. The CAN controllers are 5V devices and are supported by buffers at their interface with the 3.3V system buses provided by the logic module. The CAN controllers are configured to operate with an 8-bit non-multiplexed asynchronous host interface. Each of the CAN controllers has a 16MHz crystal that it uses for its internal clocks.

EXPIM Socket

				LK1
CAN_A[7:0]	Buffer	CAN_A[7:0]_5V
CAN_A[7:0]	U13	CAN_A[7:0]_5V		CAN1_TXD
	U13			CAN1_TXD
CAN_D[7:0]	Buffer	CAN_D[7:0]_5V	CAN		J3A
CAN_D[7:0]			CAN
			controller	U15
CAN_nOE			controller	U15
	U16		(U14)
	U16		(U14)
CAN_T/R				CAN
				CAN
CAN1_nCS		CAN1_nCS_5V		transceiver
CAN1_nCS		CAN1_nCS_5V
CAN2_nCS		CAN2_nCS_5V
CAN_R/nW	Buffer	CAN_R/nW_5V
CAN1_RESET	U17	CAN1_RESET_5V
	U17
CAN2_RESET		CAN2_RESET_5V
CAN1_TXD		CAN1_TXD_5V		LK2
				LK2
CAN2_TXD		CAN2_TXD_5V
				CAN2_TXD
CAN1_nDSACK0		CAN1_nDSACK0_5V
CAN2_nDSACK0		CAN2_nDSACK0_5V	CAN	U19	J3B
CAN2_nDSACK0	Buffer	CAN2_nDSACK0_5V	controller	U19	J3B
CAN1_nINT	Buffer		(U18)
		CAN1_nINT_5V	(U18)

				CAN
CAN2_nINT	U20	CAN2_nINT_5V		CAN
CAN2_nINT		CAN2_nINT_5V		transceiver
CAN1_RXD				transceiver
CAN1_RXD		CAN1_RXD_5V
CAN2_RXD		CAN2_RXD_5V

Figure 3-8 CAN interface architecture

3-14

Copyright © 2001-2003. All rights reserved.

ARM DUI 0163B

Image 38

Arm Enterprises IM-AD1 manual Can interface, U13, Buffer

Contents

Integrator/IM-AD1 Integrator/IM-AD1 User Guide Conformance Notices Copyright 2001-2003. All rights reserved Integrator/IM-AD1 User Guide Chapter Introduction Appendix a Signal Descriptions Preface Intended audience Using this bookAbout this book ARM publications Typographical conventionsFurther reading Third-party documents Feedback on the Integrator/IM-AD1 FeedbackFeedback on this document Xii Introduction About the Integrator/IM-AD1 ARM DUI 0163B Integrator/IM-AD1 layout Interface module features and architecture Features Integrator/IM-AD1 block diagram Architecture Config LED Links and LEDs Care of modules Introduction Copyright 2001-2003. All rights reserved Getting Started Fitting the interface module Assembled Integrator development system Setting up the logic module Switch 2 Closed Switch 3 Open Switch 4 Open Running the test software Hardware Reference Hardware Reference Uart interface Serial interface signal assignment Signal nameConnector Description Serial connector pinout Serial connector signal assignment Pin J18 Type Description SPI signals Signal SPI PWM interface signals Signal PWM interface Shows the signal assignment PWM connector signals Pin J14 J10 Description Stepper motor interface Functional description Stepper motor interface signal summary Therefore, with a 0.1Ω sense resistor fitted Stepper motor connectors Stepper motor interface signals Stepper motor connector signals Pin J19 J23 Description VSS Gpio connectors J16 and J17 Gpio Hardware Reference Buffer Can interfaceU13 Can interface signal assignment Signal IMBBANK30 IMBBANK28IMBBANK29 Can connector signal assignments Pin GND ADC and DAC interfaces 10 ADC and DAC interface architecture IMABANK50 IMABANK48IMABANK49 IMABANK51 11shows the pinout of the ADC interface connector J1 12 shows the pinout of the DAC interface connector J2 Hardware Reference Copyright 2001-2003. All rights reserved Reference Design Example Example architecture About the design exampleAbout PrimeCells Vhdl file descriptions File Description Example memory map Address assignment of logic modules Integrator system memory map Integrator/IM-AD1 memory map Device Address Integrator/IM-AD1 memory mapLogic module addresses Position Bits Stack Gpiob StepperbGpioa Ssram Offset address Name Type Function Example APB register peripheralLogic module registers Oscillator divisor registers VDW LMOSCx registers Bits Name Access FunctionRDW User LEDs control register Bits Name Access FunctionOscillator lock register Push button interrupt register Switches register Uart SPICS1 SPI chip select registerSPICS2 SPICS0 Synchronous serial port PWM controller Cont Offset Name Access Function AddressStepper motor peripheral Count Stepper x control register DIR DocountSinglestep Stepx count register Stepx speed register Data output set register Read data output pinsAddress offset Name Access Size Function Read data input register Data direction Gpio direction control 1 bit Ssram interface Interrupt Interrupt source Source number Vectored interrupt controllerInterrupt sources CAN1 Reference Design Example Can controller interface Can reset control registerCanreset CANxBase Adcstatus ADC and DAC interface16 ADC and DAC interface registers ADC2BUSY Bits Name Function Peripheral information block18 PIB entry format Signal Descriptions Expa Table A-1 AHB signal assignment Pin label Signal Description Expb Table A-2 Expb signal description Pin label Name Description Expim LM-EP20K1000E Description Table A-3 Expim signal descriptionsLabel Logic analyzer connector Figure A-4 J7 pin locations Table A-4 J7 connector pinout Signal Pin CLK1 Figure A-5 Multi-ICE connector pinout Multi-ICE Jtag Mechanical Specification Figure B-1 Board dimensions top view Mechanical information Figure B-2 Bottom board dimensions viewed from top side DB9STRAIGHT FCI Connector referenceDB9DUAL Glossary Multi-ICE Synchronous Serial Port DAC IndexADC Can Gpio Lmleds Lmlock LMOSC1 Expa A-2Gpiodataclr Gpiodatain Gpiodataout Gpiodataset Gpiodirn