IMABANK48, IMABANK49, IMABANK50, IMABANK51 | Arm Enterprises IM-AD1

Hardware Reference

Table 3-10 shows the assignment of the ADC and DAC interface signals to the logic module signals on the EXPIM connector.

Table 3-10 ADC and DAC interface signals

Signal	EXPIM connector	Description

AD_D[15:0]	IM_ABANK[47:32]	ADC and DAC data bus

AD_T/R	IM_ABANK48	Buffer direction control

AD_nOE	IM_ABANK49	Buffer output enable

ADC1_nCONV	IM_ABANK50	ADC1 conversion start signal

ADC1_nCS	IM_ABANK51	ADC1 chip select

ADC1_nWR	IM_ABANK52	ADC1 write strobe

ADC1_nRD	IM_ABANK53	ADC1 read strobe

ADC2_nCONV	IM_ABANK54	ADC2 conversion start signal

ADC2_nCS	IM_ABANK55	ADC2 chip select

ADC2_nWR	IM_ABANK56	ADC2 write strobe

ADC2_nRD	IM_ABANK57	ADC2 read strobe

ADC1_BUSY	IM_ABANK58	ADC1 busy

ADC2_BUSY	IM_ABANK59	ADC2 busy

DAC_nCLR	IM_BBANK49	DAC clear

DAC_nLDAC	IM_BBANK50	DAC load signal

DAC_A0	IM_BBANK51	DAC address bit

DAC_nCS	IM_BBANK52	DAC chip select

DAC_nWR	IM_BBANK53	DAC write strobe

ADC_CLK	IM_CLK	ADC clock

The ADCs are clocked from a 4MHz oscillator. This also supplies the IM_CLK signal routed to the logic module FPGA. This is used in the example logic to clock the DC-DC converter PrimeCell peripheral and the stepper motor interfaces.

ARM DUI 0163B

Copyright © 2001-2003. All rights reserved.

3-19

Image 43

Arm Enterprises IM-AD1 IMABANK48, IMABANK49, IMABANK50, IMABANK51, IMABANK52, IMABANK53, IMABANK54, IMABANK55, IMABANK56

Contents

Integrator/IM-AD1 User Guide Integrator/IM-AD1 Conformance Notices Copyright 2001-2003. All rights reserved Chapter Introduction Integrator/IM-AD1 User Guide Appendix a Signal Descriptions Preface About this book Using this bookIntended audience Further reading Typographical conventionsARM publications Third-party documents Feedback on this document FeedbackFeedback on the Integrator/IM-AD1 Xii Introduction ARM DUI 0163B About the Integrator/IM-AD1 Integrator/IM-AD1 layout Features Interface module features and architecture Architecture Integrator/IM-AD1 block diagram Links and LEDs Config LED Care of modules Introduction Copyright 2001-2003. All rights reserved Getting Started Assembled Integrator development system Fitting the interface module Switch 2 Closed Switch 3 Open Switch 4 Open Setting up the logic module Running the test software Hardware Reference Hardware Reference Description Serial interface signal assignment Signal nameConnector Uart interface Serial connector signal assignment Pin J18 Type Description Serial connector pinout SPI SPI signals Signal PWM interface PWM interface signals Signal PWM connector signals Pin J14 J10 Description Shows the signal assignment Functional description Stepper motor interface Therefore, with a 0.1Ω sense resistor fitted Stepper motor interface signal summary Stepper motor interface signals Stepper motor connectors VSS Stepper motor connector signals Pin J19 J23 Description Gpio Gpio connectors J16 and J17 Hardware Reference U13 Can interfaceBuffer Can interface signal assignment Signal IMBBANK29 IMBBANK28IMBBANK30 GND Can connector signal assignments Pin 10 ADC and DAC interface architecture ADC and DAC interfaces IMABANK51 IMABANK48IMABANK49 IMABANK50 11shows the pinout of the ADC interface connector J1 12 shows the pinout of the DAC interface connector J2 Hardware Reference Copyright 2001-2003. All rights reserved Reference Design Example About PrimeCells About the design exampleExample architecture File Description Vhdl file descriptions Example memory map Integrator system memory map Address assignment of logic modules Logic module addresses Position Bits Stack Integrator/IM-AD1 memory mapIntegrator/IM-AD1 memory map Device Address Ssram StepperbGpioa Gpiob Logic module registers Example APB register peripheralOffset address Name Type Function Oscillator divisor registers RDW LMOSCx registers Bits Name Access FunctionVDW Push button interrupt register Bits Name Access FunctionOscillator lock register User LEDs control register Switches register Uart SPICS0 SPI chip select registerSPICS2 SPICS1 Synchronous serial port PWM controller Count Offset Name Access Function AddressStepper motor peripheral Cont Stepper x control register Singlestep DocountDIR Stepx speed register Stepx count register Read data input register Read data output pinsAddress offset Name Access Size Function Data output set register Gpio direction control 1 bit Data direction Ssram interface CAN1 Vectored interrupt controllerInterrupt sources Interrupt Interrupt source Source number Reference Design Example CANxBase Can reset control registerCanreset Can controller interface ADC2BUSY ADC and DAC interface16 ADC and DAC interface registers Adcstatus 18 PIB entry format Peripheral information blockBits Name Function Signal Descriptions Expa Pin label Signal Description Table A-1 AHB signal assignment Expb Pin label Name Description Table A-2 Expb signal description Expim Label Table A-3 Expim signal descriptionsLM-EP20K1000E Description Figure A-4 J7 pin locations Logic analyzer connector CLK1 Table A-4 J7 connector pinout Signal Pin Multi-ICE Jtag Figure A-5 Multi-ICE connector pinout Mechanical Specification Mechanical information Figure B-1 Board dimensions top view Figure B-2 Bottom board dimensions viewed from top side DB9DUAL Connector referenceDB9STRAIGHT FCI Multi-ICE Glossary Synchronous Serial Port Gpio IndexADC Can DAC Gpiodataclr Gpiodatain Gpiodataout Gpiodataset Gpiodirn Expa A-2Lmleds Lmlock LMOSC1