LMOSCx registers Bits Name Access Function | Arm Enterprises IM-AD1

Reference Design Example

You must also observe the operating range limits:

(V[8:0] +8)

10MHz < 48MHz ·

(R[6:0] +2)

R[6:0] < 118

Table 4-5 LM_OSCx registers

Bits	Name	Access	Function

18:16	OD	Read/write	Output divider:
			000	= divide by 10
			001	= divide by 2
			010	= divide by 8
			011	= divide by 4
			100	= divide by 5
			101	= divide by 7
			110	= divide by 9
			111	= divide by 6.

15:9	RDW	Read/write	Reference divider word. Defines the binary value of
			the R[6:0] pins of the clock generator.

8:0	VDW	Read/write	VCO divider word. Defines the binary value of the
			V[8:0] pins of the clock generator.

Note

The default values for these registers set CLK1 to 25MHz and CLK2 to 12MHz.

4-10

Copyright © 2001-2003. All rights reserved.

ARM DUI 0163B

Image 56

Arm Enterprises IM-AD1 manual LMOSCx registers Bits Name Access Function, Rdw, Vdw

Contents

Integrator/IM-AD1 Integrator/IM-AD1 User Guide Conformance Notices Copyright 2001-2003. All rights reserved Integrator/IM-AD1 User Guide Chapter Introduction Appendix a Signal Descriptions Preface Intended audience Using this bookAbout this book ARM publications Typographical conventionsFurther reading Third-party documents Feedback on the Integrator/IM-AD1 FeedbackFeedback on this document Xii Introduction About the Integrator/IM-AD1 ARM DUI 0163B Integrator/IM-AD1 layout Interface module features and architecture Features Integrator/IM-AD1 block diagram Architecture Config LED Links and LEDs Care of modules Introduction Copyright 2001-2003. All rights reserved Getting Started Fitting the interface module Assembled Integrator development system Setting up the logic module Switch 2 Closed Switch 3 Open Switch 4 Open Running the test software Hardware Reference Hardware Reference Serial interface signal assignment Signal name ConnectorUart interface Description Serial connector pinout Serial connector signal assignment Pin J18 Type Description SPI signals Signal SPI PWM interface signals Signal PWM interface Shows the signal assignment PWM connector signals Pin J14 J10 Description Stepper motor interface Functional description Stepper motor interface signal summary Therefore, with a 0.1Ω sense resistor fitted Stepper motor connectors Stepper motor interface signals Stepper motor connector signals Pin J19 J23 Description VSS Gpio connectors J16 and J17 Gpio Hardware Reference Buffer Can interfaceU13 Can interface signal assignment Signal IMBBANK30 IMBBANK28IMBBANK29 Can connector signal assignments Pin GND ADC and DAC interfaces 10 ADC and DAC interface architecture IMABANK48 IMABANK49IMABANK50 IMABANK51 11shows the pinout of the ADC interface connector J1 12 shows the pinout of the DAC interface connector J2 Hardware Reference Copyright 2001-2003. All rights reserved Reference Design Example Example architecture About the design exampleAbout PrimeCells Vhdl file descriptions File Description Example memory map Address assignment of logic modules Integrator system memory map Integrator/IM-AD1 memory map Device Address Integrator/IM-AD1 memory mapLogic module addresses Position Bits Stack Stepperb GpioaGpiob Ssram Offset address Name Type Function Example APB register peripheralLogic module registers Oscillator divisor registers VDW LMOSCx registers Bits Name Access FunctionRDW Bits Name Access Function Oscillator lock registerUser LEDs control register Push button interrupt register Switches register Uart SPI chip select register SPICS2SPICS1 SPICS0 Synchronous serial port PWM controller Offset Name Access Function Address Stepper motor peripheralCont Count Stepper x control register DIR DocountSinglestep Stepx count register Stepx speed register Read data output pins Address offset Name Access Size FunctionData output set register Read data input register Data direction Gpio direction control 1 bit Ssram interface Vectored interrupt controller Interrupt sourcesInterrupt Interrupt source Source number CAN1 Reference Design Example Can reset control register CanresetCan controller interface CANxBase ADC and DAC interface 16 ADC and DAC interface registersAdcstatus ADC2BUSY Bits Name Function Peripheral information block18 PIB entry format Signal Descriptions Expa Table A-1 AHB signal assignment Pin label Signal Description Expb Table A-2 Expb signal description Pin label Name Description Expim LM-EP20K1000E Description Table A-3 Expim signal descriptionsLabel Logic analyzer connector Figure A-4 J7 pin locations Table A-4 J7 connector pinout Signal Pin CLK1 Figure A-5 Multi-ICE connector pinout Multi-ICE Jtag Mechanical Specification Figure B-1 Board dimensions top view Mechanical information Figure B-2 Bottom board dimensions viewed from top side DB9STRAIGHT FCI Connector referenceDB9DUAL Glossary Multi-ICE Synchronous Serial Port Index ADC CanDAC Gpio Lmleds Lmlock LMOSC1 Expa A-2Gpiodataclr Gpiodatain Gpiodataout Gpiodataset Gpiodirn