Arm Enterprises IM-AD1 - page 50

Reference Design Example
4-4 Copyright ©2001-2003. All rights reserved. ARM DUI 0163B
4.1.3 Example memory map
The supplied examples set up the memory map for the logic module as shown in
Figure 4-2 on page 4-5. This shows the locations to which logic modules are assigned
by the main address decoder on an Integrator/AP motherboard when the logic modules
are fitted in the EXPA/EXPB connector positions. The diagram also shows how the
example decodes the address space for the logic module when it is LM0 (bottom of the
stack).
AHBMux7S1M This is the AHB multiplexor that connects the read data buses and the HRESP and HREADY
signals from all of the slaves to the AHB master.
AHBZBTRAM An SSRAM controller block to support word, halfword, and byte operations to the SSRAM on the
logic module.
AHB2APB This is the bridge block required to connect APB peripherals to the high-speed AMBA AHB bus.
It produces the peripheral select signals for each of the APB peripherals.
APBRegs The APB register peripheral provides memory-mapped registers that you can use to:
• configure the two clock generators (protected by the LM_LOCK register)
• write to the user LEDs
• read the user switch inputs
• produce an interrupt for the LM push button.
AHBPIB This provides the ROM block that gives the following information about each peripheral:
• base address
• PrimeCell number
• peripheral revision number
• FPGA revision number.
BuildOptions This file defines generation of the PrimeCells in the example and allows control over the synthesis
so that PrimeCells can be included or excluded. It specifies the base address of all the peripherals.
GPIO32 This is a simple 32-bit GPIO block.
SPICSReg This is a simple register that is used to generate the chip selects for the SPI bus.
AHB2CAN This is the interface between the AHB and Bosch CC770 CAN devices.
AHB2AD7859 This is the interface between the AHB and the ADC and DAC converters.
Stepper This is the stepper motor controller logic, which has an APB interface.
Table4-1 VHDL file descriptions (continued)
File Description