Vhdl file descriptions, File Description | Arm Enterprises IM-AD1

Reference Design Example

System

bus

AHB

Unidirectional to bidirectional AHB interface

Default slave

Address decoder

AHB

to

APB

bridge

PIB

CAN

ADC/DAC

ZBT

SSRAM

controller

VIC

APB

Control

registers

UART

SSP

GPIO A

GPIO B

Stepper A

Stepper B

DC/DC

converter

	Figure 4-1 Design example architecture
	Table 4-1provides a summary description of the supplied VHDL files. A more detailed
	description of each VHDL block is included within the files in the form of comments.
	Table 4-1 VHDL file descriptions

File	Description

IMAD1fpga	This file is the top-level VHDL that instantiates all of the interface for the example. The VHDL for
	the PrimeCell interfaces are not supplied but are available from ARM as separate products.

AHBDecoder	The decoder provides the AHB peripherals with select line generated from the address lines and the
	module ID (position in stack) signals from the motherboard. The Integrator family of boards uses a
	distributed address decoding system (see Address assignment of logic modules on page 4-5).

AHBDefaultSlave	This block provides a default slave response when the logic module address space is addressed but
	the address does not correspond to any of the instantiated peripherals.

ARM DUI 0163B

Copyright © 2001-2003. All rights reserved.

4-3

Image 49

Arm Enterprises IM-AD1 manual Vhdl file descriptions, File Description

Contents

Integrator/IM-AD1 User Guide Integrator/IM-AD1 Conformance Notices Copyright 2001-2003. All rights reserved Chapter Introduction Integrator/IM-AD1 User Guide Appendix a Signal Descriptions Preface About this book Using this bookIntended audience Further reading Typographical conventionsARM publications Third-party documents Feedback on this document FeedbackFeedback on the Integrator/IM-AD1 Xii Introduction ARM DUI 0163B About the Integrator/IM-AD1 Integrator/IM-AD1 layout Features Interface module features and architecture Architecture Integrator/IM-AD1 block diagram Links and LEDs Config LED Care of modules Introduction Copyright 2001-2003. All rights reserved Getting Started Assembled Integrator development system Fitting the interface module Switch 2 Closed Switch 3 Open Switch 4 Open Setting up the logic module Running the test software Hardware Reference Hardware Reference Connector Serial interface signal assignment Signal nameUart interface Description Serial connector signal assignment Pin J18 Type Description Serial connector pinout SPI SPI signals Signal PWM interface PWM interface signals Signal PWM connector signals Pin J14 J10 Description Shows the signal assignment Functional description Stepper motor interface Therefore, with a 0.1Ω sense resistor fitted Stepper motor interface signal summary Stepper motor interface signals Stepper motor connectors VSS Stepper motor connector signals Pin J19 J23 Description Gpio Gpio connectors J16 and J17 Hardware Reference U13 Can interfaceBuffer Can interface signal assignment Signal IMBBANK29 IMBBANK28IMBBANK30 GND Can connector signal assignments Pin 10 ADC and DAC interface architecture ADC and DAC interfaces IMABANK49 IMABANK48IMABANK50 IMABANK51 11shows the pinout of the ADC interface connector J1 12 shows the pinout of the DAC interface connector J2 Hardware Reference Copyright 2001-2003. All rights reserved Reference Design Example About PrimeCells About the design exampleExample architecture File Description Vhdl file descriptions Example memory map Integrator system memory map Address assignment of logic modules Logic module addresses Position Bits Stack Integrator/IM-AD1 memory mapIntegrator/IM-AD1 memory map Device Address Gpioa StepperbGpiob Ssram Logic module registers Example APB register peripheralOffset address Name Type Function Oscillator divisor registers RDW LMOSCx registers Bits Name Access FunctionVDW Oscillator lock register Bits Name Access FunctionUser LEDs control register Push button interrupt register Switches register Uart SPICS2 SPI chip select registerSPICS1 SPICS0 Synchronous serial port PWM controller Stepper motor peripheral Offset Name Access Function AddressCont Count Stepper x control register Singlestep DocountDIR Stepx speed register Stepx count register Address offset Name Access Size Function Read data output pinsData output set register Read data input register Gpio direction control 1 bit Data direction Ssram interface Interrupt sources Vectored interrupt controllerInterrupt Interrupt source Source number CAN1 Reference Design Example Canreset Can reset control registerCan controller interface CANxBase 16 ADC and DAC interface registers ADC and DAC interfaceAdcstatus ADC2BUSY 18 PIB entry format Peripheral information blockBits Name Function Signal Descriptions Expa Pin label Signal Description Table A-1 AHB signal assignment Expb Pin label Name Description Table A-2 Expb signal description Expim Label Table A-3 Expim signal descriptionsLM-EP20K1000E Description Figure A-4 J7 pin locations Logic analyzer connector CLK1 Table A-4 J7 connector pinout Signal Pin Multi-ICE Jtag Figure A-5 Multi-ICE connector pinout Mechanical Specification Mechanical information Figure B-1 Board dimensions top view Figure B-2 Bottom board dimensions viewed from top side DB9DUAL Connector referenceDB9STRAIGHT FCI Multi-ICE Glossary Synchronous Serial Port ADC Can IndexDAC Gpio Gpiodataclr Gpiodatain Gpiodataout Gpiodataset Gpiodirn Expa A-2Lmleds Lmlock LMOSC1