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Arm Enterprises IM-AD1 manual Table A-1 AHB signal assignment, Pin label Signal Description

Models: IM-AD1

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Signal Descriptions

The signals present on the EXPA connector are described in Table A-1.

		Table A-1 AHB signal assignment

Pin label	Signal	Description

A[31:0]	Not used	-

B[31:0]	B[31:0]	These signals connect to the FPGA on the
		logic module. They are used to carry the
		GIPOB[31:0] signals.

C[31:0]	Not used	-

D[31:0]	Not used	-

ARM DUI 0163B

Copyright © 2001-2003. All rights reserved.

A-3

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Arm Enterprises IM-AD1 manual Table A-1 AHB signal assignment, Pin label Signal Description

Contents

Integrator/IM-AD1 User Guide Integrator/IM-AD1Conformance Notices Copyright 2001-2003. All rights reserved Chapter Introduction Integrator/IM-AD1 User GuideAppendix a Signal Descriptions Preface Intended audience Using this bookAbout this book ARM publications Typographical conventionsFurther reading Third-party documents Feedback on the Integrator/IM-AD1 FeedbackFeedback on this document Xii Introduction ARM DUI 0163B About the Integrator/IM-AD1Integrator/IM-AD1 layout Features Interface module features and architectureArchitecture Integrator/IM-AD1 block diagramLinks and LEDs Config LEDCare of modules Introduction Copyright 2001-2003. All rights reserved Getting Started Assembled Integrator development system Fitting the interface moduleSwitch 2 Closed Switch 3 Open Switch 4 Open Setting up the logic moduleRunning the test software Hardware Reference Hardware Reference Connector Serial interface signal assignment Signal nameUart interface DescriptionSerial connector signal assignment Pin J18 Type Description Serial connector pinoutSPI SPI signals SignalPWM interface PWM interface signals SignalPWM connector signals Pin J14 J10 Description Shows the signal assignmentFunctional description Stepper motor interfaceTherefore, with a 0.1Ω sense resistor fitted Stepper motor interface signal summaryStepper motor interface signals Stepper motor connectorsVSS Stepper motor connector signals Pin J19 J23 DescriptionGpio Gpio connectors J16 and J17Hardware Reference Buffer Can interfaceU13 Can interface signal assignment Signal IMBBANK30 IMBBANK28IMBBANK29 GND Can connector signal assignments Pin10 ADC and DAC interface architecture ADC and DAC interfacesIMABANK49 IMABANK48IMABANK50 IMABANK5111shows the pinout of the ADC interface connector J1 12 shows the pinout of the DAC interface connector J2 Hardware Reference Copyright 2001-2003. All rights reserved Reference Design Example Example architecture About the design exampleAbout PrimeCells File Description Vhdl file descriptionsExample memory map Integrator system memory map Address assignment of logic modulesIntegrator/IM-AD1 memory map Device Address Integrator/IM-AD1 memory mapLogic module addresses Position Bits Stack Gpioa StepperbGpiob SsramOffset address Name Type Function Example APB register peripheralLogic module registers Oscillator divisor registers VDW LMOSCx registers Bits Name Access FunctionRDW Oscillator lock register Bits Name Access FunctionUser LEDs control register Push button interrupt registerSwitches register Uart SPICS2 SPI chip select registerSPICS1 SPICS0Synchronous serial port PWM controller Stepper motor peripheral Offset Name Access Function AddressCont CountStepper x control register DIR DocountSinglestep Stepx speed register Stepx count registerAddress offset Name Access Size Function Read data output pinsData output set register Read data input registerGpio direction control 1 bit Data directionSsram interface Interrupt sources Vectored interrupt controllerInterrupt Interrupt source Source number CAN1Reference Design Example Canreset Can reset control registerCan controller interface CANxBase16 ADC and DAC interface registers ADC and DAC interfaceAdcstatus ADC2BUSYBits Name Function Peripheral information block18 PIB entry format Signal Descriptions Expa Pin label Signal Description Table A-1 AHB signal assignmentExpb Pin label Name Description Table A-2 Expb signal descriptionExpim LM-EP20K1000E Description Table A-3 Expim signal descriptionsLabel Figure A-4 J7 pin locations Logic analyzer connectorCLK1 Table A-4 J7 connector pinout Signal PinMulti-ICE Jtag Figure A-5 Multi-ICE connector pinoutMechanical Specification Mechanical information Figure B-1 Board dimensions top viewFigure B-2 Bottom board dimensions viewed from top side DB9STRAIGHT FCI Connector referenceDB9DUAL Multi-ICE GlossarySynchronous Serial Port ADC Can IndexDAC GpioLmleds Lmlock LMOSC1 Expa A-2Gpiodataclr Gpiodatain Gpiodataout Gpiodataset Gpiodirn