Stepper x control register | Arm Enterprises IM-AD1 guide

Reference Design Example

4.7.1Stepper x control register

The stepper controller control register defines the operating mode of the stepper.

Note

You must consider the maximum speed of the stepper motor when programming the step speed register or issuing consecutive single step commands in the stepper control register.

Ensure there is a delay, typically a few milliseconds, between a DOCOUNT and a SINGLESTEP. Failing to leave a delay between the end of the count and writing a SINGLESTEP command results in unpredictable behavior. The minimum duration of the delay depends on the stepper motor.

The bits in this register are described in Table 4-11.

			Table 4-11 Stepper control register

Bits	Name	Access	Function

7	BUSY	Read	This bit contains 1 when a count is in progress
			and 0 when the count is complete.

6	BUFFERFULL	Read	This bit contains 1 when the buffer is full and 0
			when the buffer is available for a new value to be
			written.
			An inverted version of this bit is used as an
			interrupt source.

5	DRIVE	Read/write	This bit enables and disables the phase outputs
	ENABLE		to the motor. When this bit is 0, ENA, ENB,
			PH1, PH2, PH3, and PH4 are held at 0. When
			this bit is 1, these signals output the relevant
			drive waveform.

4	HALFSTEP	Read/write

3	WAVEDRIVE	Read/write

These bits are used in combination to select the drive mode:

00 = Full step, two phase on (non-wave drive) drive sequence (see Figure 4-3 on page 4-19)

01 = Full step, one phase on (wave drive) drive sequence (see Figure 4-4 on page 4-19)

10 = Half step drive sequence (see Figure 4-5 on page 4-20)

11 = Reserved

4-18

Copyright © 2001-2003. All rights reserved.

ARM DUI 0163B

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Arm Enterprises IM-AD1 manual Stepper x control register

Contents

Integrator/IM-AD1 Integrator/IM-AD1 User Guide Conformance Notices Copyright 2001-2003. All rights reserved Integrator/IM-AD1 User Guide Chapter Introduction Appendix a Signal Descriptions Preface About this book Using this bookIntended audience Further reading Typographical conventionsARM publications Third-party documents Feedback on this document FeedbackFeedback on the Integrator/IM-AD1 Xii Introduction About the Integrator/IM-AD1 ARM DUI 0163B Integrator/IM-AD1 layout Interface module features and architecture Features Integrator/IM-AD1 block diagram Architecture Config LED Links and LEDs Care of modules Introduction Copyright 2001-2003. All rights reserved Getting Started Fitting the interface module Assembled Integrator development system Setting up the logic module Switch 2 Closed Switch 3 Open Switch 4 Open Running the test software Hardware Reference Hardware Reference Serial interface signal assignment Signal name ConnectorUart interface Description Serial connector pinout Serial connector signal assignment Pin J18 Type Description SPI signals Signal SPI PWM interface signals Signal PWM interface Shows the signal assignment PWM connector signals Pin J14 J10 Description Stepper motor interface Functional description Stepper motor interface signal summary Therefore, with a 0.1Ω sense resistor fitted Stepper motor connectors Stepper motor interface signals Stepper motor connector signals Pin J19 J23 Description VSS Gpio connectors J16 and J17 Gpio Hardware Reference U13 Can interfaceBuffer Can interface signal assignment Signal IMBBANK29 IMBBANK28IMBBANK30 Can connector signal assignments Pin GND ADC and DAC interfaces 10 ADC and DAC interface architecture IMABANK48 IMABANK49IMABANK50 IMABANK51 11shows the pinout of the ADC interface connector J1 12 shows the pinout of the DAC interface connector J2 Hardware Reference Copyright 2001-2003. All rights reserved Reference Design Example About PrimeCells About the design exampleExample architecture Vhdl file descriptions File Description Example memory map Address assignment of logic modules Integrator system memory map Logic module addresses Position Bits Stack Integrator/IM-AD1 memory mapIntegrator/IM-AD1 memory map Device Address Stepperb GpioaGpiob Ssram Logic module registers Example APB register peripheralOffset address Name Type Function Oscillator divisor registers RDW LMOSCx registers Bits Name Access FunctionVDW Bits Name Access Function Oscillator lock registerUser LEDs control register Push button interrupt register Switches register Uart SPI chip select register SPICS2SPICS1 SPICS0 Synchronous serial port PWM controller Offset Name Access Function Address Stepper motor peripheralCont Count Stepper x control register Singlestep DocountDIR Stepx count register Stepx speed register Read data output pins Address offset Name Access Size FunctionData output set register Read data input register Data direction Gpio direction control 1 bit Ssram interface Vectored interrupt controller Interrupt sourcesInterrupt Interrupt source Source number CAN1 Reference Design Example Can reset control register CanresetCan controller interface CANxBase ADC and DAC interface 16 ADC and DAC interface registersAdcstatus ADC2BUSY 18 PIB entry format Peripheral information blockBits Name Function Signal Descriptions Expa Table A-1 AHB signal assignment Pin label Signal Description Expb Table A-2 Expb signal description Pin label Name Description Expim Label Table A-3 Expim signal descriptionsLM-EP20K1000E Description Logic analyzer connector Figure A-4 J7 pin locations Table A-4 J7 connector pinout Signal Pin CLK1 Figure A-5 Multi-ICE connector pinout Multi-ICE Jtag Mechanical Specification Figure B-1 Board dimensions top view Mechanical information Figure B-2 Bottom board dimensions viewed from top side DB9DUAL Connector referenceDB9STRAIGHT FCI Glossary Multi-ICE Synchronous Serial Port Index ADC CanDAC Gpio Gpiodataclr Gpiodatain Gpiodataout Gpiodataset Gpiodirn Expa A-2Lmleds Lmlock LMOSC1