Programming the Board | 36 |
Overview | 36 |
Register tables | 36 |
Programming examples | 36 |
Error handling | 36 |
Initialization | 37 |
Starting the automatic initialization routine | 37 |
PCI Register | 37 |
Hardware version | 38 |
Date of production | 38 |
Serial number | 38 |
Maximum possible sample rate | 38 |
Installed memory | 38 |
Installed features and options | 39 |
Used interrupt line | 39 |
Used type of driver | 39 |
Powerdown and reset | 40 |
Analog Outputs | 41 |
Channel Selection | 41 |
Important note on channels selection | 41 |
Disabling the outputs | 41 |
Setting up the outputs | 42 |
Output Amplifiers | 42 |
Output offset | 42 |
Maximum Output Range | 43 |
Output Filters | 43 |
Standard generation modes | 44 |
General description | 44 |
Singleshot mode | 44 |
Continuous Mode | 44 |
Posttrigger Mode | 44 |
Programming | 44 |
Partitioning the memory | 44 |
Starting without interrupt (classic mode) | 46 |
Starting with interrupt driven mode | 46 |
Data organization | 47 |
Writing data with SpcSetData | 47 |
Sample format | 48 |
FIFO Mode | 49 |
Overview | 49 |
General Information | 49 |
Background FIFO Write | 49 |
Speed Limitations | 49 |
Programming | 50 |
Software Buffers | 50 |
Buffer processing | 51 |
FIFO mode | 52 |
Example FIFO generation mode | 52 |
Data organization | 52 |
Sample format | 53 |
Clock generation | 54 |
Overview | 54 |
Internally generated sample rate | 54 |
Standard internal sample rate | 54 |
Using plain quartz with no PLL | 55 |
Direct external clock | 56 |
External clock with divider | 57 |
Trigger modes and appendant registers | 58 |
General Description | 58 |
Software trigger | 58 |
External TTL trigger | 58 |
Edge triggers | 59 |
Option Multiple Replay | 61 |
Output modes | 61 |
Standard Mode | 61 |
FIFO Mode | 61 |
Trigger modes | 61 |
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