Spectrum Brands MI.61XX manual Using plain quartz with no PLL, External reference clock

Page 55

Clock generation

 

 

 

 

Internally generated sample rate

 

 

 

 

 

 

 

 

Maximum internal sample rate in MS/s normal (non FIFO) mode

 

Remapped channels

 

6110

 

6111

 

 

 

 

 

 

ch0

ch1

ch2

ch3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

x

 

 

 

 

125

 

125

 

 

x

x

 

 

 

125

 

125

 

 

x

 

x

 

 

n.a.

 

125

 

 

x

x

x

x

 

n.a.

 

125

 

Maximum internal sample rate in MS/s in FIFO mode

 

Remapped channels

 

6110

 

6111

 

 

 

 

 

 

ch0

ch1

ch2

ch3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

x

 

 

 

 

125

 

125

 

 

x

x

 

 

 

125

 

125

 

 

x

 

x

 

 

n.a.

 

125

 

 

x

x

x

x

 

n.a.

 

60

 

Using plain quartz with no PLL

In some cases it is useful for the application not to have the on-board PLL activated. Although the PLL used on the Spectrum boards is a low- jitter version it still produces more clock jitter than a plain quartz oscillator. For these cases the Spectrum boards have the opportunity to switch off the PLL by software and use a simple clock divider.

Register

Value

Direction

Description

SPC_PLL_ENABLE

20030

r/w

A „1“ enables the PLL mode (default) or disables it by writing a 0 to this register

The sample rates that could be set are then limited to the quartz speed divided by one of the below mentioned dividers. The quartz used on the board is similar to the maximum sample rate the board can achieve. As with PLL mode it’s also possible to set a desired sample rate and read it back. The result will then again be the best matching sample rate.

Available divider values

1

2

4

8

10

16

20

40

50

80

100

200

400

500

800

1000

2000

 

 

 

 

 

 

 

External reference clock

Register

Value

Direction

Description

SPC_REFERENCECLOCK

20140

r/w

Programs the external reference clock in the range from 1 MHz to 125 MHz.

 

0

 

Internal reference is used for internal sample rate generation.

 

External sample rate in Hz as an integer value

External reference is used. You need to set up this register exactly to the frequency of the external fed in clock.

If you have an external clock generator with a extremly stable frequency, you can use it as a reference clock. You can connect it to the external clock connector and the PLL will be fed with this clock instead of the internal reference. Due to the fact that the driver needs to know the external fed in frequency for an exact calculation of the sample rate you must set the the SPC_REFERENCECLOCK register accordingly. The driver automatically sets the PLL to achieve the desired sample rate. Therefore it examines the reference clock and the sample rate registers.

Example of reference clock:

SpcSetParam (hDrv, SPC_EXTERNAL,

0);

// Set to internal

clock

SpcSetParam

(hDrv,

SPC_REFERENCECLOCK,

10000000);

//

Reference clock

that is fed in is 10 MHz

SpcSetParam

(hDrv,

SPC_SAMPLERATE,

25000000);

//

We want to have

25 MHz as sample rate

Termination of the clock input

If the external connector is used as an input, either for feeding in an external reference clock or for external clocking you can enable a 50 Ohm termination on the board. If the termination is disabled, the impedance is 1 Megaohm. Please make sure that your source is capable of driving that current and that it still fulfills the clock input specification as given in the technical data section.

Register

Value

Direction

Description

SPC_CLOCK50OHM

20120

r/w

A „1“ enables the 50 Ohm termination at the external clock connector. Only possible, when using

 

 

 

the external connector as an input.

External clocking

(c) Spectrum GmbH

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Image 55
Contents English version October 5 MI.61xxPage Software Hardware InstallationSoftware Driver Installation IntroductionStandard generation modes Fifo ModeProgramming the Board Analog OutputsAppendix Option Gated ReplayOption Extra I/O Synchronization OptionPreface IntroductionPreface General InformationMI.6110 MI.6111 Different models of the MI.61xx seriesIntroduction Extra I/O Option -XMF Additional optionsExtra I/O Option -XIO Introduction Additional options StarhubSpectrum type plate Hardware information Block diagram Technical DataFilter Dynamic ParametersOrder information Hardware informationIntroductionInstalling the board in the system Hardware InstallationSystem Requirements Installing a board with extra I/O Option -XMF Installing a board with digital inputs/outputsOnly use the included flat ribbon cables Installing multiple boards synchronized by starhubMounting the wired boards Hooking up the boardsInstalling multiple synchronized boards Software Driver Installation Software Driver InstallationInterrupt Sharing Windows InstallationVersion control Driver Update Windows Software Driver Installation Windows Windows XP Windows XP Adding boards to the Windows NT driver Windows NTOverview LinuxAutomatic load of the driver Installing the deviceNow it is possible to access the board using this device Driver infoSoftware SoftwareSoftware Overview First Test with SBenchLinux Gnu C ++ Driver InterfaceHeader files Microsoft Visual C++Include Drivers Other Windows C/C++ compilersNational Instruments LabWindows/CVI Driver functionsFunction SpcGetData Function SpcSetParamFunction SpcSetParam Function SpcSetData WindowsSpectrum GmbH Examples Delphi Pascal Programming InterfaceType definition Include DriverDelphi Pascal Programming Interface Visual Basic Examples Visual Basic Programming InterfaceVBA for Excel Examples Visual Basic Programming Interface Register tables Error handlingProgramming the Board OverviewPCI Register Example for error checkingInitialization Starting the automatic initialization routineSerial number Installed memoryHardware version Date of productionDriver version Installed features and optionsUsed interrupt line Used type of driverSpcpciserialno Powerdown and resetExample program for the board initialization SpcpcimemsizeDisabling the outputs Analog OutputsChannel Selection Important note on channels selectionRegister Value Direction Description Amplitude range Setting up the outputsOutput Amplifiers Output offsetMaximum Output Range Filter SpecificationsOutput Filters General description Standard generation modesProgramming Minimum and stepsize of memsize and posttrigger in samples Standard generation modes ProgrammingMaximum memsize Maximum posttrigger in MSamplesProgrammingStandard generation modes Starting without interrupt classic modeStarting with interrupt driven mode Command registerValue ’len’ as a 32 bit integer value Data organizationWriting data with SpcSetData Value ’start’ as a 32 bit integer valueBit Standard Mode Standard modeSample format Speed Limitations Fifo ModeGeneral Information Background Fifo Write60040 Read out the number of available Fifo buffers Programming Fifo ModeSoftware Buffers Theoretical maximum sample rate PCI Bus ThroughputDigital I/O 701x or 702x or pattern generator boards Fifo Mode ProgrammingBuffer processing Analog acquisition or generation boardsSpcfifowait Example Fifo generation mode== Maxbuf SpcfifostartProgramming Internally generated sample rate Clock generationStandard internal sample rate External reference clock Using plain quartz with no PLLExternal clocking Minimum external sample rate Direct external clockMaximum external samplerate in MS/s Example External clock with dividerCHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 External TTL trigger Example for setting up the software triggerTrigger modes and appendant registers Software triggerPositive TTL trigger Example on how to set up the board for positive TTL triggerEdge triggers Trigger modes and appendant registersPositive and negative TTL trigger Trigger modes Standard ModeOption Multiple Replay Output modesTrigger modes Option Multiple Replay Resulting start delaysValue Direction Description General information and trigger delayOption Gated Replay Option Gated ReplaySpctriggermode Tmttlpos Example programAllowed trigger modes External TTL edge triggerTransfer Data Option Extra I/ODigital I/Os Channel directionProgramming example Analog OutputsAnalog Outputs Option Extra I/O Synchronization with option starhub Synchronization OptionDifferent synchronization options Synchronization with option cascadingWrite Data to on-board memory output boards only Setup order for the different synchronization optionsSet up the board parameters Example of board setup for three boardsDefine the remaining boards as trigger slaves Define the boards for trigger masterExample of board #2 set as trigger master 3a Define synchronization or triggerArm the boards for synchronization Define the board for clock masterExample board number 0 is clock master Define the remaining boards as clock slavesExample for data reading Start all of the trigger master boardsWait for the end of the measurement Read data from the on-board memory acquisition boards onlySpcsyncslavefifo Allocate the Fifo software buffers2a Write first data for output boards SpcsyncmasterfifoAs trigger slaves 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx Additions for synchronizing different boardsGeneral information Calculating the clock dividersBoard type 3025 3131 Setting up the clock dividerBoard type 3122 3120 40 MS/sAdditions for equal boards with different sample rates Resulting delays using different boards or speedsDelay in standard non Fifo modes Delay in Fifo modeAppendix Error CodesError name Value hex Value dec Error description AppendixExtra I/O with external connectorOption -XMF Pin assignment of the multipin connectorPin assignment of the multipin cable D15 D13 D11 Pin assignment of the internal multipin connectorExtra I/O with internal connector Option -XIO D14 D12 D10