Marvel Group 88F6281 manuals
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Marvel Group 88F6281 Specifications
140 pages 1.12 Mb
88F6281Integrated ControllerHardware Specifications2 Document ConventionsNote: Provides related information or information of special importance. Caution: Indicates potential damage to hardware or software, or loss of data. Warning: Indicates a risk of personal injury. Document StatusDoc Status: Preliminary Technical Publication: 0.xx For more information, visit our website at: www.marvell.com 88F6281 3 88F6281Integrated ControllerXOR Engine Hardware Specifications PRODUCT OVERVIEWSheeva Processor Memory Security Engine High Speed I/0 88F6281 Functional Block Diagram Misc Gigabit Ethernet IEEE 1588AVB support Media Interfaces 4 FEATURESFeatures 7 88F6281x16 x8 TDM Usage Model Example: VoIP Gateway 8 Table of Contents10 List of Tables13 List of Figures15 PrefaceAbout this Document Related DocumentationSee the Marvell Extranet website for the latest product documentation. 16 Document ConventionsThe following conventions are used in this document: 88F6281 18 1.1 Pin LogicPCI Express MPP JTAG SATA0/1 SDRAM Gigabit Ethernet USB Power Misc. Figure 1: 88F6281 Pin Logic Diagram NOTE:The GE_TXCLKOUT pin is an input only when used as the MII/MMII Transmit Clock. NAND Flash 19 1.2 Pin Descriptions Table 1: Pin Functions and Assignments Table Key Table 2: Interface Pin Prefix Codes 21 1.2.1 Power Supply PinsTable 3: Power Pin Assignments 22 88F6281 Table 3: Power Pin Assignments (Continued) 23 1.2.2 Miscellaneous Pin AssignmentThe Miscellaneous signal list contains clock and reset, test, and related signals. Table 4: Miscellaneous Pin Assignments 88F6281 24 1.2.3 DDR SDRAM Interface Pin Assignments 26 1.2.4 PCI Express Interface Pin AssignmentsTable 6: PCI Express Interface Pin Assignments 27 1.2.5 SATA Interface Pin AssignmentsTable 7: SATA Port Interface Pin Assignment 88F6281 28 1.2.6 Gigabit Ethernet Port Interface Pin Assignments Table 8: Gigabit Ethernet Port0/1 Interface Pin Assignments 88F6281 32 1.2.7 Serial Management Interface (SMI) Interface Pin Assignments Table 9: Serial Management Interface (SMI) Pin Assignments 33 1.2.8 USB 2.0 Interface Pin Assignments34 1.2.9 JTAG Interface Pin AssignmentTable 11: JTAG Pin Assignment 35 1.2.10 Real Time Clock (RTC) Interface Pin Assignments36 1.2.11 NAND Flash Interface Pin Assignment Table 13: NAND Flash Interface Pin Assignment 37 1.2.12 MPP Interface Pin Assignment Table 14: MPP Interface Pin AssignmentThe various functionalities of the MPP pins are detailed in 88F6281 38 1.2.13 Two-Wire Serial Interface (TWSI) InterfaceAll of the TWSI signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing, Table 15: Two-Wire Serial Interface (TWSI) Interface Pin Assignment 39 1.2.14 UART InterfaceTable 16: UART Port 0/1 Interface Pin Assignment 88F6281 40 1.2.15 Audio (S/PDIF / I2S) Interface1. Fs is the audio sample rate. Multiplexing, on page 51). multiplexing option. Table 17: Audio (S/PDIF / I2S) Interface Signal Assignment 41 1.2.16 Serial Peripheral Interface (SPI) Interface Table 18: Serial Peripheral Interface (SPI) Interface Signal Assignment 88F6281 42 1.2.17 Secure Digital Input/Output (SDIO) Interface All of the SDIO signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing, Table 19: Secure Digital Input/Output (SDIO) Interface Signal Assignment 43 1.2.18 Time Division Multiplexing (TDM) InterfaceMultiplexing, on page51). multiplexing option (see Section 4, Pin Multiplexing, on page 51). Table 20: Time Division Multiplexing (TDM) Interface Signal Assignment 44 88F6281 Table 20: Time Division Multiplexing (TDM) Interface Signal Assignment (Continued) 45 1.2.19 Transport Stream (TS) InterfaceMultiplexing, on page51). multiplexing option (see Section 4, Pin Multiplexing ). Table 21: Transport Stream (TS) Interface Signal Assignment 46 88F6281 Table 21: Transport Stream (TS) Interface Signal Assignment (Continued) 47 1.2.20 Precise Timing Protocol (PTP) Interface Table 22: Precise Timing Protocol (PTP) Interface Signal Assignment 88F6281 48 1.3 Internal Pull-up and Pull-down PinsTable 23: Internal Pull-up and Pull-down Pins Unused Interface Strapping 49 2Table 24: Unused Interface Strapping 50 3To open the attached Excel pin list file, double-click the pin icons below: 51 460 563 6Settings6.1 Power-Up/Down Sequence Requirements6.1.1 Power-Up Sequence RequirementsTable 31: I/O and Core Voltages 88F6281 Figure 2: Power-Up Sequence Example 6.1.2 Power-Down Sequence Requirements 64 6.2 Hardware Reset66 6.3 PCI Express Reset6.3.1 PCI Express Root Complex Reset 6.3.2 PCI Express Endpoint Reset 6.4 Sheeva CPU TAP Controller Reset 6.5 Pins Sample Configuration 70 6.6 Serial ROM InitializationFigure 3: Serial ROM Data Structure 6.6.1 Serial ROM Data Structure 6.6.2 Serial ROM Initialization OperationFigure 4: Serial ROM Read Example 71 6.7 Boot Sequence 73 77.1 TAP Controller 7.2 Instruction RegisterTable 33: Supported JTAG Instructions 88F6281 74 7.3 Bypass Register7.4 JTAG Scan Chain 7.5 ID RegisterTable 34: IDCODE Register Map 75 8129 9Table 72: Thermal Data for the 88F6281 in the BGA 19 x 19 mm Package (Preliminary) 130 10 131 PackageTable 73: HSBGA 288-pin Package Dimensions 88F6281 132 11 11.1 Part Order NumberingFigure 48: Sample Part Number xxBIA2Cxxxxxxx 88F6281Table 74: 88F6281 Part Order Options Part Order Numbering/Package Marking 133 11.2 Package MarkingFigure 49 shows a sample Commercial package marking and pin 1 location for the 88F6281. Figure 49: Commercial Package Marking and Pin 1 Location 88F6-BIAe Lot Number YYWW xx@ Country of Origin 88F6281-xx XXXX 134 A
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