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Texas Instruments 28xxx Manual

Texas Instruments 28xxx Manual

119 pages1.01 Mb

3Contents
- Preface
9Read This First
- Related Documentation From Texas Instruments
- 11Trademarks
- Chapter 1
13Introduction
- 141.1 Introduction
- 1.2 Submodule Overview
  - Submodule Overview
  - 15Figure 1-1. Multiple ePWM Modules
- 171.3 Register Mapping
  - Register Mapping
    - SPRU791D November 2004 Revised October 2007 Introduction 17Submit Documentation Feedback
  - Figure 1-3. ePWM Submodules and Critical Internal Signal Interconnects
  - Register Mapping
  - 18Table 1-1. ePWM Module Control and Status Register Set Grouped by Submodule
- Chapter 2
19ePWM Submodules
- 202.1 Overview
  - Overview
- 232.2 Time-Base (TB) Submodule
- 2.2.1 Purpose of the Time-Base Submodule
- 242.2.2 Controlling and Monitoring the Time-base Submodule
- 252.2.3 Calculating PWM Period and Frequency
  - 262.2.3.1 Time-Base Period Shadow Register
  - Figure 2-3. Time-Base Frequency and Period
  - 28Scheme 3, shown in Figure 2-6 , is used by all other devices.
- 302.2.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
- 2.2.5 Time-base Counter Modes and Timing Waveforms
  - 31Figure 2-8. Time-Base Down-Count Mode Waveforms
  - Figure 2-9. Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down On SynchronizationEvent
- 322.3 Counter-Compare (CC) Submodule
  - Figure 2-10. Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up On SynchronizationEvent
  - Figure 2-12 shows the basic structure of the counter-compare submodule.
- 332.3.1 Purpose of the Counter-Compare Submodule
- 2.3.2 Controlling and Monitoring the Counter-Compare Submodule
  - Figure 2-12. Detailed View of the Counter-Compare Submodule
- 342.3.3 Operational Highlights for the Counter-Compare Submodule
- 2.3.4 Count Mode Timing Waveforms
  - 35Figure 2-14. Counter-Compare Events in Down-Count Mode
- 372.4 Action-Qualifier (AQ) Submodule
- 2.4.1 Purpose of the Action-Qualifier Submodule
- 2.4.2 Action-Qualifier Submodule Control and Status Register Definitions
- 402.4.3 Action-Qualifier Event Priority
- 412.4.4 Waveforms for Common Configurations
  - 45Example 2-3. Code Sample for Figure 2-22
  - Figure 2-23. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation onEPWMxA
- 502.5 Dead-Band Generator (DB) Submodule
- 2.5.1 Purpose of the Dead-Band Submodule
- 2.5.2 Controlling and Monitoring the Dead-Band Submodule
  - Dead-Band Generator (DB) Submodule
- 512.5.3 Operational Highlights for the Dead-Band Submodule
  - 53Dead-Band Generator (DB) Submodule
- 552.6 PWM-Chopper (PC) Submodule
- 2.6.1 Purpose of the PWM-Chopper Submodule
- 2.6.3 Operational Highlights for the PWM-Chopper Submodule
- 2.6.2 Controlling the PWM-Chopper Submodule
  - mnemonic Address offset Shadowed Description PCCTL 0x001E No PWM-chopper Control Register
- 562.6.4 Waveforms
  - PSCLK
  - EPWMxB
  - Figure 2-31. PWM-Chopper Submodule Operational Details
  - 582.6.4.2 Duty Cycle Control
- 592.7 Trip-Zone (TZ) Submodule
- 2.7.1 Purpose of the Trip-Zone Submodule
- 602.7.2 Controlling and Monitoring the Trip-Zone Submodule
- 2.7.3 Operational Highlights for the Trip-Zone Submodule
- 622.7.4 Generating Trip Event Interrupts
  - Trip-Zone (TZ) Submodule
- 632.8 Event-Trigger (ET) Submodule
  - Figure 2-37. Trip-Zone Submodule Interrupt Logic
- 642.8.1 Operational Overview of the Event-Trigger Submodule
  - 67Figure 2-42. Event-Trigger SOCA Pulse Generator
- Chapter 3
69Applications to Power Topologies
- 703.1 Overview of Multiple Modules
- 3.2 Key Configuration Capabilities
- 713.3 Controlling Multiple Buck Converters With Independent Frequencies
  - Figure 3-2. EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave
  - 72Figure 3-3. Control of Four Buck Stages. Here F
    - NOTE: = X indicates value in phase register is a "don't care"
  - 73Figure 3-4. Buck Waveforms for Figure 3-3 (Note: Only three bucks shown here)
- 753.4 Controlling Multiple Buck Converters With Same Frequencies
- 783.5 Controlling Multiple Half H-Bridge (HHB) Converters
  - Controlling Multiple Half H-Bridge (HHB) Converters
  - = N x F
    - Controlling Multiple Half H-Bridge (HHB) Converters
  - 79Figure 3-8. Half-H Bridge Waveforms for Figure 3-7 (Note: Here F
- 803.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
  - www.ti.com
  - Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
  - 81Figure 3-9. Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control
    - Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
  - 82Figure 3-10. 3-Phase Inverter Waveforms for Figure 3-9 (Only One Inverter Shown)
- 843.7 Practical Applications Using Phase Control Between PWM Modules
  - Practical Applications Using Phase Control Between PWM Modules
  - Figure 3-11. Configuring Two PWM Modules for Phase Control
- 853.8 Controlling a 3-Phase Interleaved DC/DC Converter
  - Controlling a 3-Phase Interleaved DC/DC Converter
  - 86Figure 3-13. Control of a 3-Phase Interleaved DC/DC Converter
    - Controlling a 3-Phase Interleaved DC/DC Converter
  - 87Figure 3-14. 3-Phase Interleaved DC/DC Converter Waveforms for Figure 3-13
- 893.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
  - Figure 3-15. Controlling a Full-H Bridge Stage (F
  - 90Figure 3-16. ZVS Full-H Bridge Waveforms
  - 91Example 3-6. Code Snippet for Configuration in Figure 3-15
- Chapter 4
93Registers
- 944.1 Time-Base Submodule Registers
  - Time-Base Submodule Registers
  - 95Figure 4-4. Time-Base Control Register (TBCTL)
  - Table 4-4. Time-Base Control Register (TBCTL) Field Descriptions
    - Time-Base Submodule Registers
  - 96Table 4-4. Time-Base Control Register (TBCTL) Field Descriptions (continued)
- 974.2 Counter-Compare Submodule Registers
  - Counter-Compare Submodule Registers
  - Figure 4-5. Time-Base Status Register (TBSTS)
  - Table 4-5. Time-Base Status Register (TBSTS) Field Descriptions
  - Counter-Compare Submodule Registers
  - 98Table 4-6. Counter-Compare A Register (CMPA) Field Descriptions
  - Figure 4-7. Counter-Compare B Register (CMPB)
  - Table 4-7. Counter-Compare B Register (CMPB) Field Descriptions
- 994.3 Action-Qualifier Submodule Registers
  - Figure 4-8. Counter-Compare Control Register (CMPCTL)
  - Table 4-8. Counter-Compare Control Register (CMPCTL) Field Descriptions
  - 100Figure 4-9. Action-Qualifier Output A Control Register (AQCTLA)
  - Table 4-9. Action-Qualifier Output A Control Register (AQCTLA) Field Descriptions
  - 101Figure 4-10. Action-Qualifier Output B Control Register (AQCTLB)
  - Table 4-10. Action-Qualifier Output B Control Register (AQCTLB) Field Descriptions
  - 102Figure 4-11. Action-Qualifier Software Force Register (AQSFRC)
  - Table 4-11. Action-Qualifier Software Force Register (AQSFRC) Field Descriptions
  - Figure 4-12. Action-Qualifier Continuous Software Force Register (AQCSFRC)
- 1034.4 Dead-Band Submodule Registers
  - Dead-Band Submodule Registers
  - Table 4-12. Action-qualifier Continuous Software Force Register (AQCSFRC) Field Descriptions
  - Dead-Band Submodule Registers
  - 104Table 4-13. Dead-Band Generator Control Register (DBCTL) Field Descriptions
- 1054.5 PWM-Chopper Submodule Control Register
  - PWM-Chopper Submodule Control Register
  - Figure 4-14. Dead-Band Generator Rising Edge Delay Register (DBRED)
  - Table 4-14. Dead-Band Generator Rising Edge Delay Register (DBRED) Field Descriptions
  - Figure 4-15. Dead-Band Generator Falling Edge Delay Register (DBFED)
  - Table 4-15. Dead-Band Generator Falling Edge Delay Register (DBFED) Field Descriptions
  - Table 4-16. PWM-Chopper Control Register (PCCTL) Bit Descriptions
- 1064.6 Trip-Zone Submodule Control and Status Registers
  - Table 4-16. PWM-Chopper Control Register (PCCTL) Bit Descriptions (continued)
  - Figure 4-17 and Table 4-17 provide the trip-zone control and status register definitions.
  - 107Figure 4-17. Trip-Zone Select Register (TZSEL)
  - Table 4-17. Trip-Zone Submodule Select Register (TZSEL) Field Descriptions
  - 108Table 4-17. Trip-Zone Submodule Select Register (TZSEL) Field Descriptions (continued)
  - Figure 4-18. Trip-Zone Control Register (TZCTL)
  - Table 4-18. Trip-Zone Control Register (TZCTL) Field Descriptions
  - Figure 4-19. Trip-Zone Enable Interrupt Register (TZEINT)
  - Table 4-19. Trip-Zone Enable Interrupt Register (TZEINT) Field Descriptions
  - 109Table 4-19. Trip-Zone Enable Interrupt Register (TZEINT) Field Descriptions (continued)
  - Figure 4-20. Trip-Zone Flag Register (TZFLG)
  - Table 4-20. Trip-Zone Flag Register (TZFLG) Field Descriptions
- 1104.7 Event-Trigger Submodule Registers
  - Figure 4-21. Trip-Zone Clear Register (TZCLR)
  - Table 4-21. Trip-Zone Clear Register (TZCLR) Field Descriptions
  - Figure 4-22. Trip-Zone Force Register (TZFRC)
  - Table 4-22. Trip-Zone Force Register (TZFRC) Field Descriptions
  - 111Figure 4-23. Event-Trigger Selection Register (ETSEL)
  - Table 4-23. Event-Trigger Selection Register (ETSEL) Field Descriptions
  - 112Table 4-23. Event-Trigger Selection Register (ETSEL) Field Descriptions (continued)
  - Figure 4-24. Event-Trigger Prescale Register (ETPS)
  - Table 4-24. Event-Trigger Prescale Register (ETPS) Field Descriptions
  - 113Table 4-24. Event-Trigger Prescale Register (ETPS) Field Descriptions (continued)
  - Figure 4-25. Event-Trigger Flag Register (ETFLG)
  - 114Table 4-25. Event-Trigger Flag Register (ETFLG) Field Descriptions
  - Figure 4-26. Event-Trigger Clear Register (ETCLR)
  - Table 4-26. Event-Trigger Clear Register (ETCLR) Field Descriptions
- 1154.8 Proper Interrupt Initialization Procedure
- Appendix A
117Revision History
- Appendix A
- 118Table A-1. Changes for Revision D (continued)
- 119IMPORTANT NOTICE

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