Name Description | Texas Instruments TMS320x28xx, 28xxx specification

www.ti.com

Event-Trigger Submodule Registers

Table 4-23. Event-Trigger Selection Register (ETSEL) Field Descriptions (continued)

Bits	Name	Value	Description
2-0	INTSEL		ePWM Interrupt (EPWMx_INT) Selection Options
		000	Reserved
		001	Enable event time-base counter equal to zero. (TBCTR = 0x0000)
		010	Enable event time-base counter equal to period (TBCTR = TBPRD)
		011	Reserved
		100	Enable event time-base counter equal to CMPA when the timer is incrementing.
		101	Enable event time-base counter equal to CMPA when the timer is decrementing.
		110	Enable event: time-base counter equal to CMPB when the timer is incrementing.
		111	Enable event: time-base counter equal to CMPB when the timer is decrementing.

Figure 4-24. Event-Trigger Prescale Register (ETPS)

15	14	13	12	11	10	9	8
	SOCBCNT		SOCBPRD		SOCACNT		SOCAPRD
	R-0		R/W-0		R-0		R/W-0
7			4	3	2	1	0
	Reserved				INTCNT		INTPRD
	R-0				R-0		R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-24. Event-Trigger Prescale Register (ETPS) Field Descriptions

Bits	Name	Description
15-14	SOCBCNT	ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Counter Register
		These bits indicate how many selected ETSEL[SOCBSEL] events have occurred:
	00	No events have occurred.
	01	1 event has occurred.
	10	2 events have occurred.
	11	3 events have occurred.
13-12	SOCBPRD	ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Period Select
		These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an
		EPWMxSOCB pulse is generated. To be generated, the pulse must be enabled
		(ETSEL[SOCBEN] = 1). The SOCB pulse will be generated even if the status flag is set from
		a previous start of conversion (ETFLG[SOCB] = 1). Once the SOCB pulse is generated, the
		ETPS[SOCBCNT] bits will automatically be cleared.
	00	Disable the SOCB event counter. No EPWMxSOCB pulse will be generated
	01	Generate the EPWMxSOCB pulse on the first event: ETPS[SOCBCNT] = 0,1
	10	Generate the EPWMxSOCB pulse on the second event: ETPS[SOCBCNT] = 1,0
	11	Generate the EPWMxSOCB pulse on the third event: ETPS[SOCBCNT] = 1,1
11-10	SOCACNT	ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Counter Register
		These bits indicate how many selected ETSEL[SOCASEL] events have occurred:
	00	No events have occurred.
	01	1 event has occurred.
	10	2 events have occurred.
	11	3 events have occurred.

112

Registers

SPRU791D–November 2004–Revised October 2007

Submit Documentation Feedback

Image 112

Texas Instruments TMS320x28xx, 28xxx manual Event-Trigger Prescale Register Etps Field Descriptions, Name Description

Contents

Reference Guide Submit Documentation Feedback Contents Controlling a 3-Phase Interleaved DC/DC Converter List of Figures Event-Trigger Socb Pulse Generator Simplified ePWM Module List of Tables Submit Documentation Feedback Related Documentation From Texas Instruments Data ManualsCPU Users Guides Peripheral Guides Tools Guides Application Reports Trademarks TMS320C28x, C28x are trademarks of Texas Instruments Submit Documentation Feedback Introduction Introduction Submodule Overview Multiple ePWM Modules ∙ PWM output signals EPWMxA and EPWMxB ∙ Trip-zone signals TZ1 to TZ6∙ ADC start-of-conversion signals EPWMxSOCA and EPWMxSOCB ∙ Peripheral Bus EPWM Submodules and Critical Internal Signal Interconnects Register Mapping Offset Size Name DescriptionTime-Base Submodule Registers Counter-Compare Submodule Registers EPWM Submodules Submodule Configuration Parameter or Option Submodule Configuration ParametersOverview Example 2-1. Constant Definitions Used in the Code Examples Tbup Chpenable Time-Base TB Submodule Purpose of the Time-Base Submodule Time-Base Submodule Registers Controlling and Monitoring the Time-base SubmoduleRegister Key Time-Base Signals ∙ Up-Down-Count Mode∙ Up-Count Mode ∙ Down-Count Mode ∙ Time-Base Period Shadow Mode ∙ Time-Base Period Immediate Load ModeTime-Base Period Shadow Register ∙ Active Register Time-Base Counter Synchronization Time-Base Counter Synchronization Scheme EPWM11SYNCI EPWM11SYNCO ∙ EPWMxSYNCI Synchronization Input Pulse ∙ Software Forced Synchronization Pulse Phase Locking the Time-Base Clocks of Multiple ePWM Modules Time-base Counter Modes and Timing Waveforms Time-Base Down-Count Mode Waveforms Counter-Compare CC Submodule 11. Counter-Compare Submodule Purpose of the Counter-Compare Submodule Controlling and Monitoring the Counter-Compare SubmoduleCounter-Compare Submodule Registers Register Name Address Offset Count Mode Timing Waveforms Counter-Compare Submodule Key Signals∙ Shadow Mode ∙ Immediate Load Mode CTR=CMPA CTR=CMPB CTR = Cmpb Purpose of the Action-Qualifier Submodule Action-Qualifier AQ SubmoduleAction-Qualifier Submodule Registers Action-Qualifier Submodule Possible Input Events ∙ Set High∙ Clear Low ∙ Toggle TB Counter equals Actions Action-Qualifier Event Priority for Up-Down-Count Mode Action-Qualifier Event Priority for Up-Count Mode10. Action-Qualifier Event Priority for Down-Count Mode Action-Qualifier Event Priority Waveforms for Common Configurations Use up-down-count mode to generate a symmetric PWMUse up-down-count mode to generate an asymmetric PWM When using up-count mode to generate an asymmetric PWM 20. Up-Down-Count Mode Symmetrical Waveform Example 2-2. Code Sample for Figure Tbctr Value EPWMxA EPWMxB Example 2-3. Code Sample for Figure Tbclk = Sysclkout Example 2-4. Code Sample for Figure EdgePosA Example 2-5. Code Sample for Figure Example 2-6. Code Sample for Figure Tbctr Example 2-7. Code Sample for Figure EPWMxA EPWMxB Dead-Band Generator DB Submodule Purpose of the Dead-Band SubmoduleControlling and Monitoring the Dead-Band Submodule 12. Dead-Band Generator Submodule Registers ∙ Output Mode Control Operational Highlights for the Dead-Band Submodule∙ Input Source Selection ∙ Polarity Control Mode Description 13. Classical Dead-Band Operating Modes 29. Dead-Band Waveforms for Typical Cases 0% Duty 100% Dead-Band Delay in μS FED = Dbfed × Ttbclk RED = Dbred × Ttbclk PWM-Chopper PC Submodule Purpose of the PWM-Chopper SubmoduleControlling the PWM-Chopper Submodule Operational Highlights for the PWM-Chopper Submodule Waveforms 31. PWM-Chopper Submodule Operational Details 16. Possible Pulse Width Values for Sysclkout = 100 MHz One-Shot PulseOSHTWTHz Duty Cycle Control Period Trip-Zone TZ Submodule Purpose of the Trip-Zone Submodule Controlling and Monitoring the Trip-Zone Submodule Operational Highlights for the Trip-Zone Submodule17. Trip-Zone Submodule Registers ∙ Cycle-by-Cycle CBC Example 2-8. Trip-Zone Configurations 18. Possible Actions On a Trip EventScenario a Scenario B 36. Trip-Zone Submodule Mode Control Logic Generating Trip Event Interrupts Event-Trigger ET Submodule 37. Trip-Zone Submodule Interrupt Logic Operational Overview of the Event-Trigger Submodule 19. Event-Trigger Submodule Registers CTR=CMPB CTRD=CMPB 41. Event-Trigger Interrupt Generator 42. Event-Trigger Soca Pulse Generator Submit Documentation Feedback Applications to Power Topologies Controlling Multiple Buck Converters With Independent Key Configuration Capabilities Overview of Multiple Modules CTR=0 EPWM1B CTR=CMPB Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 Buck Waveforms for -3Note Only three bucks shown here Example 3-1. Configuration for Example in Figure 500 Controlling Multiple Buck Converters With Same Frequencies Control of Four Buck Stages. Note FPWM2 = N x FPWM1 Buck Waveforms for -5Note FPWM2 = FPWM1 Example 3-2. Code Snippet for Configuration in Figure Controlling Multiple Half H-Bridge HHB Converters Control of Two Half-H Bridge Stages FPWM2 = N x FPWM1 Half-H Bridge Waveforms for -7Note Here FPWM2 = FPWM1 Controlling Dual 3-Phase Inverters for Motors ACI and Pmsm Example 3-3. Code Snippet for Configuration in Figure EPWM1A 10 -Phase Inverter Waveforms for -9Only One Inverter Shown Example 3-4. Code Snippet for Configuration in Figure 11. Configuring Two PWM Modules for Phase Control Controlling a 3-Phase Interleaved DC/DC Converter Controlling a 3-Phase Interleaved DC/DC Converter 13. Control of a 3-Phase Interleaved DC/DC Converter 14 -Phase Interleaved DC/DC Converter Waveforms for Figure Example 3-5. Code Snippet for Configuration in Figure 15. Controlling a Full-H Bridge Stage FPWM2 = FPWM1 16. ZVS Full-H Bridge Waveforms Example 3-6. Code Snippet for Configuration in Figure Submit Documentation Feedback PWM-Chopper Submodule Control Register Proper Interrupt Initialization ProcedureTrip-Zone Submodule Control and Status Registers Time-Base Phase Register Tbphs Field Descriptions Time-Base Submodule RegistersTime-Base Period Register Tbprd Field Descriptions Time-Base Counter Register Tbctr Field Descriptions Time-Base Control Register Tbctl Field Descriptions Bit Field Value Description Software Forced Synchronization Pulse Time-Base Status Register Tbsts Field Descriptions Counter-Compare Submodule RegistersBit Field Counter-Compare B Register Cmpb Field Descriptions Counter-Compare a Register Cmpa Field DescriptionsBits Name Description Action-Qualifier Submodule Registers Counter-Compare Control Register Cmpctl Field Descriptions Bits Name CBD CBU CAD CAU PRD ZROCBD 10. Action-Qualifier Output B Control Register Aqctlb Rldcsf Rldcsf Otsfb Actsfb Otsfa ActsfaCsfb Csfa Csfb Dead-Band Submodule RegistersInmode Polsel Outmode Inmode PWM-Chopper Submodule Control Register 16. PWM-Chopper Control Register Pcctl Bit DescriptionsName Value Description Reserved PWM-Chopper Control Register Pcctl Bit Descriptions Trip-Zone Submodule Control and Status RegistersChpduty OSHT6 OSHT5 OSHT4 OSHT3 OSHT2 OSHT1 CBC6 CBC5 CBC4 CBC3 CBC2 CBC1OSHT6 CBC6 18. Trip-Zone Control Register Tzctl Field Descriptions TZB TZATZB OST CBC 20. Trip-Zone Flag Register Tzflg Field Descriptions OST CBC INT 21. Trip-Zone Clear Register Tzclr Field Descriptions Event-Trigger Submodule Registers22. Trip-Zone Force Register Tzfrc Field Descriptions 23. Event-Trigger Selection Register Etsel 24. Event-Trigger Prescale Register Etps Field Descriptions Name Description 24. Event-Trigger Prescale Register Etps Field Descriptions Socb Soca 26. Event-Trigger Clear Register Etclr Field Descriptions 25. Event-Trigger Flag Register Etflg Field DescriptionsSocb Proper Interrupt Initialization Procedure 27. Event-Trigger Force Register Etfrc Field Descriptions 116 Table A-1. Changes for Revision D Location Modifications, Additions, and Deletions Appendix a Important Notice