CTR=0 EPWM1B CTR=CMPB | Texas Instruments 28xxx, TMS320x28xx

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Controlling Multiple Buck Converters With Independent Frequencies

Figure 3-2. EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave

	Ext SyncIn
	(optional)
Master
	SyncIn
Phase reg EN
Φ=0°	EPWM1A
	EPWM1A
CTR=0	EPWM1B
CTR=0
CTR=CMPB
X
1	SyncOut

Slave

Phase reg	SyncIn
	EN
Φ=0°

CTR=0

CTR=CMPB X

2SyncOut

EPWM2A

EPWM2B

3.3Controlling Multiple Buck Converters With Independent Frequencies

One of the simplest power converter topologies is the buck. A single ePWM module configured as a master can control two buck stages with the same PWM frequency. If independent frequency control is required for each buck converter, then one ePWM module must be allocated for each converter stage. Figure 3-3shows four buck stages, each running at independent frequencies. In this case, all four ePWM modules are configured as Masters and no synchronization is used. Figure 3-4shows the waveforms generated by the setup shown in Figure 3-3; note that only three waveforms are shown, although there are four stages.

SPRU791D–November 2004–Revised October 2007

Applications to Power Topologies

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Texas Instruments 28xxx, TMS320x28xx manual CTR=0 EPWM1B CTR=CMPB

Contents

Reference Guide Submit Documentation Feedback Contents Controlling a 3-Phase Interleaved DC/DC Converter List of Figures Event-Trigger Socb Pulse Generator Simplified ePWM Module List of Tables Submit Documentation Feedback Peripheral Guides Related Documentation From Texas InstrumentsData Manuals CPU Users Guides Application Reports Tools Guides TMS320C28x, C28x are trademarks of Texas Instruments Trademarks Submit Documentation Feedback Introduction Submodule Overview Introduction Multiple ePWM Modules ∙ Peripheral Bus ∙ PWM output signals EPWMxA and EPWMxB∙ Trip-zone signals TZ1 to TZ6 ∙ ADC start-of-conversion signals EPWMxSOCA and EPWMxSOCB Register Mapping EPWM Submodules and Critical Internal Signal Interconnects Counter-Compare Submodule Registers Offset Size NameDescription Time-Base Submodule Registers EPWM Submodules Overview Submodule Configuration ParametersSubmodule Configuration Parameter or Option Tbup Example 2-1. Constant Definitions Used in the Code Examples Chpenable Purpose of the Time-Base Submodule Time-Base TB Submodule Register Controlling and Monitoring the Time-base SubmoduleTime-Base Submodule Registers ∙ Down-Count Mode Key Time-Base Signals∙ Up-Down-Count Mode ∙ Up-Count Mode ∙ Active Register ∙ Time-Base Period Shadow Mode∙ Time-Base Period Immediate Load Mode Time-Base Period Shadow Register Time-Base Counter Synchronization Scheme Time-Base Counter Synchronization EPWM11SYNCO EPWM11SYNCI ∙ Software Forced Synchronization Pulse ∙ EPWMxSYNCI Synchronization Input Pulse Time-base Counter Modes and Timing Waveforms Phase Locking the Time-Base Clocks of Multiple ePWM Modules Time-Base Down-Count Mode Waveforms 11. Counter-Compare Submodule Counter-Compare CC Submodule Register Name Address Offset Purpose of the Counter-Compare SubmoduleControlling and Monitoring the Counter-Compare Submodule Counter-Compare Submodule Registers ∙ Immediate Load Mode Count Mode Timing WaveformsCounter-Compare Submodule Key Signals ∙ Shadow Mode CTR=CMPB CTR=CMPA CTR = Cmpb Action-Qualifier Submodule Registers Action-Qualifier AQ SubmodulePurpose of the Action-Qualifier Submodule ∙ Toggle Action-Qualifier Submodule Possible Input Events∙ Set High ∙ Clear Low TB Counter equals Actions Action-Qualifier Event Priority Action-Qualifier Event Priority for Up-Down-Count ModeAction-Qualifier Event Priority for Up-Count Mode 10. Action-Qualifier Event Priority for Down-Count Mode When using up-count mode to generate an asymmetric PWM Waveforms for Common ConfigurationsUse up-down-count mode to generate a symmetric PWM Use up-down-count mode to generate an asymmetric PWM 20. Up-Down-Count Mode Symmetrical Waveform Tbctr Example 2-2. Code Sample for Figure Value EPWMxA EPWMxB Tbclk = Sysclkout Example 2-3. Code Sample for Figure EdgePosA Example 2-4. Code Sample for Figure Example 2-5. Code Sample for Figure Tbctr Example 2-6. Code Sample for Figure EPWMxA EPWMxB Example 2-7. Code Sample for Figure 12. Dead-Band Generator Submodule Registers Dead-Band Generator DB SubmodulePurpose of the Dead-Band Submodule Controlling and Monitoring the Dead-Band Submodule ∙ Polarity Control ∙ Output Mode ControlOperational Highlights for the Dead-Band Submodule ∙ Input Source Selection 13. Classical Dead-Band Operating Modes Mode Description 29. Dead-Band Waveforms for Typical Cases 0% Duty 100% FED = Dbfed × Ttbclk RED = Dbred × Ttbclk Dead-Band Delay in μS Operational Highlights for the PWM-Chopper Submodule PWM-Chopper PC SubmodulePurpose of the PWM-Chopper Submodule Controlling the PWM-Chopper Submodule 31. PWM-Chopper Submodule Operational Details Waveforms OSHTWTHz One-Shot Pulse16. Possible Pulse Width Values for Sysclkout = 100 MHz Period Duty Cycle Control Purpose of the Trip-Zone Submodule Trip-Zone TZ Submodule ∙ Cycle-by-Cycle CBC Controlling and Monitoring the Trip-Zone SubmoduleOperational Highlights for the Trip-Zone Submodule 17. Trip-Zone Submodule Registers Scenario B Example 2-8. Trip-Zone Configurations18. Possible Actions On a Trip Event Scenario a Generating Trip Event Interrupts 36. Trip-Zone Submodule Mode Control Logic 37. Trip-Zone Submodule Interrupt Logic Event-Trigger ET Submodule Operational Overview of the Event-Trigger Submodule CTR=CMPB CTRD=CMPB 19. Event-Trigger Submodule Registers 41. Event-Trigger Interrupt Generator 42. Event-Trigger Soca Pulse Generator Submit Documentation Feedback Controlling Multiple Buck Converters With Independent Applications to Power Topologies Overview of Multiple Modules Key Configuration Capabilities CTR=0 EPWM1B CTR=CMPB Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 Buck Waveforms for -3Note Only three bucks shown here 500 Example 3-1. Configuration for Example in Figure Control of Four Buck Stages. Note FPWM2 = N x FPWM1 Controlling Multiple Buck Converters With Same Frequencies Buck Waveforms for -5Note FPWM2 = FPWM1 Example 3-2. Code Snippet for Configuration in Figure Control of Two Half-H Bridge Stages FPWM2 = N x FPWM1 Controlling Multiple Half H-Bridge HHB Converters Half-H Bridge Waveforms for -7Note Here FPWM2 = FPWM1 Example 3-3. Code Snippet for Configuration in Figure Controlling Dual 3-Phase Inverters for Motors ACI and Pmsm EPWM1A 10 -Phase Inverter Waveforms for -9Only One Inverter Shown Example 3-4. Code Snippet for Configuration in Figure 11. Configuring Two PWM Modules for Phase Control Controlling a 3-Phase Interleaved DC/DC Converter Controlling a 3-Phase Interleaved DC/DC Converter 13. Control of a 3-Phase Interleaved DC/DC Converter 14 -Phase Interleaved DC/DC Converter Waveforms for Figure Example 3-5. Code Snippet for Configuration in Figure 15. Controlling a Full-H Bridge Stage FPWM2 = FPWM1 16. ZVS Full-H Bridge Waveforms Example 3-6. Code Snippet for Configuration in Figure Submit Documentation Feedback Trip-Zone Submodule Control and Status Registers Proper Interrupt Initialization ProcedurePWM-Chopper Submodule Control Register Time-Base Counter Register Tbctr Field Descriptions Time-Base Phase Register Tbphs Field DescriptionsTime-Base Submodule Registers Time-Base Period Register Tbprd Field Descriptions Bit Field Value Description Time-Base Control Register Tbctl Field Descriptions Software Forced Synchronization Pulse Bit Field Counter-Compare Submodule RegistersTime-Base Status Register Tbsts Field Descriptions Bits Name Description Counter-Compare a Register Cmpa Field DescriptionsCounter-Compare B Register Cmpb Field Descriptions Counter-Compare Control Register Cmpctl Field Descriptions Action-Qualifier Submodule Registers CBD CBD CBU CAD CAU PRD ZROBits Name 10. Action-Qualifier Output B Control Register Aqctlb Csfb Csfa Rldcsf Otsfb Actsfb Otsfa ActsfaRldcsf Inmode Polsel Outmode Dead-Band Submodule RegistersCsfb Inmode Reserved PWM-Chopper Submodule Control Register16. PWM-Chopper Control Register Pcctl Bit Descriptions Name Value Description Chpduty Trip-Zone Submodule Control and Status RegistersPWM-Chopper Control Register Pcctl Bit Descriptions CBC6 OSHT6 OSHT5 OSHT4 OSHT3 OSHT2 OSHT1CBC6 CBC5 CBC4 CBC3 CBC2 CBC1 OSHT6 OST CBC 18. Trip-Zone Control Register Tzctl Field DescriptionsTZB TZA TZB OST CBC INT 20. Trip-Zone Flag Register Tzflg Field Descriptions 22. Trip-Zone Force Register Tzfrc Field Descriptions Event-Trigger Submodule Registers21. Trip-Zone Clear Register Tzclr Field Descriptions 23. Event-Trigger Selection Register Etsel Name Description 24. Event-Trigger Prescale Register Etps Field Descriptions Socb Soca 24. Event-Trigger Prescale Register Etps Field Descriptions Socb 25. Event-Trigger Flag Register Etflg Field Descriptions26. Event-Trigger Clear Register Etclr Field Descriptions 27. Event-Trigger Force Register Etfrc Field Descriptions Proper Interrupt Initialization Procedure 116 Location Modifications, Additions, and Deletions Table A-1. Changes for Revision D Appendix a Important Notice